K66 - PLL Clock source

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K66 - PLL Clock source

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Masmiseim
Senior Contributor I

Hello,

 

I have a question about the Kinetis K66 controller. You can switch the input clock of the PLL between the System Oscillator and the IRC48M (labelled at the picture). But where can I configure the switch. Sorry for the trivial question, but I couldn’t find the register to configure it.

 

Thanks and regards

K66 Clock.png

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Markus,

You can find the description in the sections"27.1.1 MCG oscillator clock input options" of K66P144M180SF5RMV2.

MCG oscillator clock input options.png

After double-click the "OSCSEL PLL", the "IRC 48MHz" can be selected.

Clock Tool.png

Best Regards,

Robin

 

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1,399件の閲覧回数
Masmiseim
Senior Contributor I

Hey,

 

thanks for the reply.

I thought also in this direction as it would be similar to other Kinetis controllers. But the Online Clock-Tool had confused me again. You can configure both switches independently:

K66 Clock tool.png

 

Maybe a misleading Image in the Reference manual plus a Bug in the clock tool?

Regards

1,400件の閲覧回数
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Markus,

You can find the description in the sections"27.1.1 MCG oscillator clock input options" of K66P144M180SF5RMV2.

MCG oscillator clock input options.png

After double-click the "OSCSEL PLL", the "IRC 48MHz" can be selected.

Clock Tool.png

Best Regards,

Robin

 

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
---------------------------------------------------------------------------------------------------------------------

1,399件の閲覧回数
Masmiseim
Senior Contributor I

Hello Robin,

 

So, the two switches in the Flow-Diagram are actually one single switch like Mark already mentioned.

 

Thanks for the confirmation.

 

Regards

 

Markus

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mjbcswitzerland
Specialist V

Hi Markus

I am not 100% sure, but think that the image is misleading - I think that PRDIV is in fact connected to the same signal as FRDIV, meaning that the source is selected by MCG_C7.

See the following too:
http://www.utasker.com/kinetis/MCG.html
whereby they are shown as connected.

Possibly the additional gate is there to "signify" that only two settings of the three are actually 'workable' for the PLL input (which can't use the 32k input).

Another diagram in the K66 manual show the selected using the same switch:

pastedImage_2.png

Regards

Mark