Incorrect DDR2 configuration in TOWER defaults

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Incorrect DDR2 configuration in TOWER defaults

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bjoernjohanness
Contributor III

The default DDR configuration for the tower project sets

     DDR_CR21 = 0x20040232

More specifically it clears MR1DAT0 bit E11, which means that DQS# is enabled (See DDR UM: EMR definition). This is incorrect since the Kinetis DRAM controller only supports single-ended DQS. Right??

I'm extremely surprised no one else has mentioned this in the community, probably due to the extremely poor documentation of the DRAM controller so people just give up.

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bjoernjohanness
Contributor III

Update: Since Ma Hui has no interest in replying with the correct answer, I'll provide it to whoever is interested:

As mentioned, turns out that the TOWER project ("K70 DDR2 configuration tool" etc.) is incorrectly configured. Freescale now acknowledges this. Bit E10 in EMR1 should be SET rather than cleared in order to disable DQS#, which physically isn't supported by Kinetis. Hence, something like this is in order:

DDR_CR21 = 0x20040232  |  (1 << (10+16) );

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

K70 DDR2 Controller only support single-ended DQS. As I check TWR-K70F120M board DDR2 initialization code with below setting about DDR_CR21:

DDR_CR21 = 0x00040232;

So, the DDR2 memory still keep the default DQS# setting, which default is disable.

Wish it helps.
best regards
Ma Hui

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66 Views
bjoernjohanness
Contributor III

Update: Since Ma Hui has no interest in replying with the correct answer, I'll provide it to whoever is interested:

As mentioned, turns out that the TOWER project ("K70 DDR2 configuration tool" etc.) is incorrectly configured. Freescale now acknowledges this. Bit E10 in EMR1 should be SET rather than cleared in order to disable DQS#, which physically isn't supported by Kinetis. Hence, something like this is in order:

DDR_CR21 = 0x20040232  |  (1 << (10+16) );

View solution in original post

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bjoernjohanness
Contributor III

Ma, thank you for your reply. I appreciate it.

Could you please take a second to elaborate how you reach that conclusion? Which of the 32 bits in 0x00040232 will keep the DDR2 memory in it's "default DQS# setting"?

Thanks!

//bjoern

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