How to initialize I2S as a slave in FRDM_K22F

negarerfanian · ‎07-29-2015

Hi,

I'm working with FRDM_K22F and I just initialized I2C as a master and connected K22F to WM8731 CODEC. the next step that I'm gonna do is to initialize I2S in K22F as a slave so that it receives data from ADC port of CODEC and after that send this data to transmitter and transmit it to DAC port of CODEC.

My problem is that as I searched a lot in the internet I don't know exactly how to use FIFO without interrupt or DMA to know when data is ready in the receiver and send it to transmitter.

Can anyone help me with this issue?

Thanks,

xiangjun_rong · ‎07-30-2015

Hi, Negar,

I suggest you use PE to generate the code to initialize the I2S module. Regarding your question to use FIFO, as you know that the both the receiver and transmitter have 8*32 bits FIFO for K22 family, in other words, both the receiver and transmitter have 8 deep FIFO, using FIFO can save the core load. For example, you use interrupt mechanism to read data from receiver, if you do not use FIFO, once the receiver get one data, an interrupt from IIS receiver will will be triggered so that the Core can read the data to a memory. If you use receiver FIFO, for example, you set the watermark in I2Sx_RCR1 as 6, only the IIS receiver get 6 data, the corresponding FRF flag in I2Sx_RCSR is set, if you enable the FIFO interrupt by setting the FRIE bit in I2Sx_RCSR, an interrupt will be triggered, in the ISR, you can read 6 data from receiver FIFO, obviously, it will save core load.

Both the Codewarriopr for mcu ver10.6 and KDS all support PE.

Hope it can help you

BR

Xiangjun Rong

View solution in original post

xiangjun_rong · ‎07-30-2015

Hi, Negar,

I suggest you use PE to generate the code to initialize the I2S module. Regarding your question to use FIFO, as you know that the both the receiver and transmitter have 8*32 bits FIFO for K22 family, in other words, both the receiver and transmitter have 8 deep FIFO, using FIFO can save the core load. For example, you use interrupt mechanism to read data from receiver, if you do not use FIFO, once the receiver get one data, an interrupt from IIS receiver will will be triggered so that the Core can read the data to a memory. If you use receiver FIFO, for example, you set the watermark in I2Sx_RCR1 as 6, only the IIS receiver get 6 data, the corresponding FRF flag in I2Sx_RCSR is set, if you enable the FIFO interrupt by setting the FRIE bit in I2Sx_RCSR, an interrupt will be triggered, in the ISR, you can read 6 data from receiver FIFO, obviously, it will save core load.

Both the Codewarriopr for mcu ver10.6 and KDS all support PE.

Hope it can help you

BR

Xiangjun Rong

xiangjun_rong · ‎07-30-2015

This is PE screenshot of IIS module using KDS tools.

BR

Xiangjun Rong

negarerfanian · ‎07-30-2015

Hi xiangjun,

Actually I am using PE but I was not using SSI_LDD. I was using init_I2S. now I'm gonna change it.

The problem is that after I initialize it I want to receive data and send it to transmitter. First I need to enable both transmitter and receiver . what about channels? Shall I enable them too?

another thing that I was considering is that I'm checking FRF bit to see if it's 1, it will put data from receiver data register into transmitter data register. but it seems that it's never set. am I doing sth wrong?

Regards,