sure, but I did it long time ago, Here is the codes for reference:
Initialization and application
To initialize DMA multiple pulse counting capability. We need to perform following step:
For DMA module:
- Enable DMAMUX and DMA clock and configure DMAMUX request source.
- Set DMA source and destination address to a dummy variable address.
- Set DMA source and destination minor and major address adjustment and offset to zero.
- Set each DMA channel’s countdown counter(CITER, BITER) to proper value;
- Enable DMA channel request to wait peripheral trigger signal.
For GPIO and PORT module:
- Set PORT pin mux to GPIO
- Enable DMA rising/falling request on PORT_MUX register.
For Application:
- Initializing DMA and GPIO module.
- Read DMA channel counters value in application to get pulse count value.
Reference code:
Uint32_t dummy;
/* clock gate initialization */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK,
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK,
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK,
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK,
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK,
/* set pin to GPIO function and enable DMA request source */
PORTA->PCR[0] |= PORT_PCR_MUX(1)| PORT_PCR_IRQC(1);
PORTA->PCR[0] |= PORT_PCR_MUX(1)| PORT_PCR_IRQC(1);
PORTA->PCR[0] |= PORT_PCR_MUX(1)| PORT_PCR_IRQC(1);
PORTA->PCR[0] |= PORT_PCR_MUX(1)| PORT_PCR_IRQC(1);
PORTA->PCR[0] |= PORT_PCR_MUX(1)| PORT_PCR_IRQC(1);
/* enable DMA and DMAMUX clock */
SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;
Before configuring DMA MUX trigger and source number, the DMAMUX->CFG[ENBL]
bit should be disabled.
/* clears register for changing source and trigger */
DMAMUX->CHCFG[1] = 0;
DMAMUX->CHCFG[2] = 0;
DMAMUX->CHCFG[3] = 0;
DMAMUX->CHCFG[4] = 0;
/* set DMA channel request source */
DMAMUX->CHCFG[0]= DMA MUX_CHCFG_ENBL_MASK| DMA MUX_CHCFG_SOURCE(49);
DMAMUX->CHCFG[1]= DMA MUX_CHCFG_ENBL_MASK| DMA MUX_CHCFG_SOURCE(50);
DMAMUX->CHCFG[2]= DMA MUX_CHCFG_ENBL_MASK| DMA MUX_CHCFG_SOURCE(51);
DMAMUX->CHCFG[3]= DMA MUX_CHCFG_ENBL_MASK| DMA MUX_CHCFG_SOURCE(52);
DMAMUX->CHCFG[4]= DMA MUX_CHCFG_ENBL_MASK| DMA MUX_CHCFG_SOURCE(53);
Before initializing DMA register, define the source data and the address of source and destination.
DMA module initialization (only take DMA channel 0 for example)
/* source configuration */
DMA0->TCD[0].SADDR = &dummy;
DMA0->TCD[0].ATTR = DMA_ATTR_SSIZE(0);
DMA0->TCD[0].SOFF= 0; /* no address shift after each transfer */
DMA0->TCD[0].SLAST = 0;
/* destination configuration */
DMA0->TCD[0].DADDR = &dummy;
DMA0->TCD[0].ATTR = DMA_ATTR_DSIZE(0);
DMA0->TCD[0].DOFF= 0;
DMA0->TCD[0].DLAST_SGA= 0;
/* set CITER and BITER to maximum value */
DMA0->TCD[0].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER_MASK;
DMA0->TCD[0].BITER_ELINKNO = DMA_CITER_ELINKNO_BITER_MASK;
DMA0->TCD[0].NBYTES_MLNO = 1; /* transfer one byte on each trigger arrived */
/* enable auto close requirement */
DMA0->TCD[0].CSR |= DMA_CSR_DREQ_MASK;
/* start transfer */
DMA0->SERQ = DMA_SERQ_SERQ(0);
Read DMA channel counter in your application, pulse counting value is BITER minus CITER:
Uint32_t value;
value = DMA0->TCD[0]. BITER_ELINKNO - DMA0->TCD[0].CITER_ELINKN