Hi Mark Brinkman,
Yes, it is 20.971MHz, my mistyping.

You can consider the T3 on the above picture should be at least 128 bus clock cycles.
That document is from the KE series. in the K series, please refer to the reference manual, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash
initialization has completed.
The picture is give your a reference. You can consider T3 should at least 128 bus clock, it is for the flash initialization.
Wish it helps you!
If you still have question, please let me know!
Have a great day,
Kerry
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