ARM errata 838869

[LArmstrong1985]

Sometimes I came across this type of note in the examples.

What is it due this error?

What does the __DSB () statement do to prevent it and when is it needed?

Thank you very much

[ErichStyger]

There is a good explanation in http://www.ti.com/lit/er/swrz078b/swrz078b.pdf  of the underlying ARM errata. To my knowledge it affects all Cortex-M4 devices (but not sure as I have not found the original information on ARM.com). Basically if there is a store immediate with offset at the end of the ISR this could lead to incorrect interrupt handling. That DSB instruction is a data synchronization barrier instruction which makes sure that any pending memory accesses in the write buffer gets executed (kind of 'flush' for the data pending to be written).

ARM rates this situation as 'rare', but such store immediate could be generated by the compiler if accessing for example peripheral registers. In my own exprience I had applications which crashed once every few days for unknown reasons. After I have added such a DSB at the end of every ISR the crashes disappeared and I have applications running for >6 months now without a single problem or crash. So while the problem depends on how interrupts are executed and what code is inside the ISR, I highly recommend to have this DSB added to the exit of every ISR. FreeRTOS has this added in the Cortex-M ports for years already, even if it was not marked as 'not necessary', but indeed its preventing a possible problem in the kernel too.

I hope this helps,

Erich

[LArmstrong1985]

Thank you very much Erich.

I will follow your advice to put this instruction at the end of each

interrupt callback.

Fabio

Il 27/03/2020 15:54, ErichS ha scritto:

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Re: ARM errata 838869

reply from Erich Styger

<https://community.nxp.com/people/ErichS?et=watches.email.thread> in

/Kinetis Microcontrollers/ - View the full discussion

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[mjbcswitzerland]

Hi

See also the following for a practical problem when the data barrier is not used and how it solves it. The data barrier use is not always needed - it depends on what the routine actually does and how long it takes to do it... It is not actually Errata#838869 but it shows how data synchronisation may be important.

Why does the eDMA ISR get called twice after one major count completion interrupt? 

Regards

Mark

[uTasker project developer for Kinetis and i.MX RT]