Device Boot Mode sequence for K32L2B31VFM0A

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Device Boot Mode sequence for K32L2B31VFM0A

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Nikunj
Contributor II

HI,

Can you provide a Boot Mode sequence timing diagram? if not possible then please suggest how much time we have to put a logic low level on reset and boot config[NMI] pin.

 

Thanks

Nikunj

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3 Replies

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jingpan
NXP TechSupport
NXP TechSupport

Hi Nikunj,

Reset has two type, POR reset and other reset source reset, include reset pin reset.

If it's a POR reset, you'd better keep reset pin low till VDD arrive at 1.8V, 1.54v at least. After that LVD will hold reset signal till 1.8V. After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction is 300us.

jingpan_0-1606290253240.png

 

If it's a reset pin reset,  reset pin should be hold over 1 bus clock. Reset pin can use filter. Please see 6.2.2.1.1 in reference manual.

To make system stable, you should pull-up reset pin with a 4.7k~10k resistor. And don't connect capacitor to NMI pin.

 

Regards,

Jing

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Nikunj
Contributor II

HI,

we are using 9600 baudrate for UART. There is no application firmware inside the device,we observe that if firmware loading is stopped due to some issue we have to always erase the device using j link flash. Then after we receive a valid ping response and the firmware loading is complete inside the device.

Please suggest how to resume firmware load in the device if in boot mode using host((nRF52840) the first time. 

Thanks

-Nikunj

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Nikunj
Contributor II

Hi,

can you provide a low-level time period for the BootCFG[NMI] pin?

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