MCG Fails To Lock After MCGC2 Changed

[R_R_Ritchey]

I am running on the MCF51JM32 with an external crystal.  If the external crystal fails to start I need to keep running on the internal reference.  My problem is that I change MCGC2 to start the external crystal and if the OSCINIT fails to go true I change MCGC2 back to 0x00 to disable the external oscillator.  When I do this I get a loss of lock and the lock bit goes false. I clear the loss-of-lock but I cannot get the FLL to re-lock to the internal reference.  I have tried re-writing some registers to maybe get the FLL to try to lock again but nothing.  I can tell the FLL is not locked because its running at about 40MHz when I have the internal reference and DRS set to run at 48MHz. 

This is posted in the Coldfire forum but I think it applies to any processor with the MCG.

Anyone know a solution to this? 

[R_R_Ritchey]

OK, I found the answer.  For some inexplicable reason the OSCINIT logic seems to be tied to the LOCK and LOSS-of-LOCK logic.  I was trying to simulate the fact that the OSCINIT timer timed out by just ignoring that OSCINIT went true and jumping to the clock recovery routine.  Turns out I had to physically disable the crystal for this to work right.  Once the crystal was disabled, OSCINIT would not go true and the timer really timed out.  Setting MCGC2 back to zero did not cause the LOSS-of-LOCK to go true and LOCK go false.

[TomE]

I don't have a solution, but I have some questions.

The MCG in this chip has an FLL and a PLL. Has anyone seen anything describing WHY you might run with one or the other? What can one do that the other can't?

Searching for "MCG PLL FLL" on this site brings up a lot of matches. Have you found anything useful in any of them? This one looks interesting:

https://community.nxp.com/message/454295?commentID=454295#comment-454295

I've been looking for relevant App Notes, but can only find ones like this for an S08. It details the IGC and the MCG, and says when (and how) to use an FLL vs a PLL:

http://cache.nxp.com/docs/en/application-note/AN3499.pdf?fsrch=1&sr=3&pageNum=1

Are you following the "permitted mode transitions" in "7.4.2 MCG Mode State Diagram"?

Can you try and lock the PLL to the Crystal and maybe not upset the FLL as much?

Tom

[R_R_Ritchey]

The USB can only run on the PLL.   I can successfully get from FEI to PEE.  I follow the steps in the reference manual explicitly.  The issue here is that if I cannot start the External Reference (bad crystal, etc) then I need to keep using the FLL.  To do this the MCGC2 register is set to start the crystal which has absolutely nothing to do with the FLL.  It does not change anything in the FLL path.  The FLL keeps running but when I try to reset the MCGC2 register back to 0x00 to disable the External Reference (which did not start anyway) the FLL lock goes away.  I did not fine anything helpful in the references.  Thanks for taking time to reply.