Hi Amit,
MCG mode switch is using below ways: from FEI to PEE
Wish it helps.
best regards
Ma Hui
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Amit
The following code shows how to set 48MHz system clock with 24MHz bus and flash clocks.
There is no cde there that is not relevant to this task and the defines used should be more understandable that the ones in the PE generated code. I have also written the hex values that are actually programmed to the registers so that you can compare with the user manual's register descriptions.
MCG_C2 = (MCG_C2_RANGE_1M_8M | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator [0x14]
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_256); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used) [0x98]
while (!(MCG_S & MCG_S_OSCINIT)) {} // loop until the crystal source has been selected
while (MCG_S & MCG_S_IREFST) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes [0x23]
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS); // [0x40]
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {}// loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides [0x00110000]
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024); // finally move from PBE to PEE mode - switch to PLL clock [0x28]
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected
When using a crystal the loading resistors and capacitors in the circuit are important since the oscillator gain must be set to mathc - if it doesn't match the ocillator may not start. In the case of the FRDM-K20D50M the loading is low so the gain must be set to low (MCG_C2_GAIN_MODE is 0). The code is taken from the uTasker project which allows simple configuration and will warn in case of setting anything out of range. It's simulator shows the achieved settinmgs when it runs. The user level setup for the FRDM-K20D50M is as follows:
#define OSC_LOW_GAIN_MODE // oscillator without feedback resistor or load capacitors so use low gain mode
#define CRYSTAL_FREQUENCY 8000000 // 8 MHz crystal
#define CLOCK_DIV 4 // input must be divided to 2MHz..4MHz range (/1 to /25 possible)
#define CLOCK_MUL 24 // the PLL multiplication factor to achieve system/core operating frequency of 48MHz (x24 to x55 possible)
#define BUS_CLOCK_DIVIDE 1 // bus clock without divide for 48MHz
#define FLASH_CLOCK_DIVIDE 2 // flash clock divided by 2 for 24MHz
#define USB_CLOCK_GENERATED_INTERNALLY // use USB clock from internal source rather than external pin
As you can see, it is very simple to adjust any settings without needing to get involved with the values to put in the registers themselves.
Below is the simulator showing the operation with these settings.
The project includes configurations for almost every Freescale development board (KE, KL and K series) and the simulator will accurately verify just about all processor types.
Regards
Mark
Hi Mark
Thanks for the concise code. I will go through this and try to get the related info. Meanwhile I found this fig.
I realized that the config I want to do is the last one i.e PEE. so such huge process is required .
Kind Regards
Amit
