Clock Trim Help?

[nijaju]

Hey,

I'm trying to figure out how all of this clock trimming stuff works. I've read through a few threads and don't see the answer to my question, but if anyone knows where it is out there, please point me to it. I'm new at this.

I have two ColdFire MCF51QE64 chips that I'm playing with. I'm using the internal clock and need a fairly accurate 4MHz Bus Clock. Using PWM, I'm throw the Bus Clock divided by 1000 (MHz to KHz) out to a pin that I measure with a meter to determine the actual speed of the Bus Clock. With ColdFire chip 1, I've determined that ICSTRM needs to be 0xB7 to get a 4MHz Bus Clock. For ColdFire chip 2, ICSTRM needs to be 0xA1. If I understand how this is supposed to work, there is some non-volatile (NV) storage at address 0x3FF which is supposed to hold this chip specific value. Then, all I need to do is copy the value from that location into ICSTRM and I get my nice 4MHz Clock. I don't understand how I'm supposed to program 0xA1 and 0xB7 into address 0x3FF of the respective chips so that it can be used at runtime. (For simplicity in describing my situation, I've omitted the fact that there's also 1 bit at ICSSC_FTRIM which has an accompanying NV bit at address 0x0x3FE).

Are the tools supposed to program these NV addresses for me? If so, how do they know what value to put in or do I enter the value? This seems like a very handy mechanism but I feel like I'm missing some key piece of information which brings it all together. Any help would be appreciated.

Thanks,

Nick

[TomE]

From the Reference Manual:

12.4.6 Internal Reference Clock

All MCU devices are factory programmed with a trim value in a reserved memory location. This value is
uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer
precision, you can trim the internal oscillator in the application and set the FTRIM bit accordingly.

4.2.1 Flash Module Reserved Memory Locations

The factory trim values are stored in the flash information row (IFR)1 and are automatically loaded into
the ICSTRM and ICSSC registers after any reset. The oscillator trim values stored in TRIM and FTRIM
can be reprogrammed by third party programmers and must be copied into the corresponding ICS registers
(ICSTRM and ICSSC) by user code to override the factory trim.

                                 NOTE
When the MCU is in active BDM, the trim value in the IFR is not loaded.
Instead, the ICSTRM register resets to 0x80 and ICSSC[FTRIM] resets to
zero.

IFR — Nonvolatile information memory that can only be accessed during production test. During production test, system
initialization, configuration, and test information is stored in the IFR. This information cannot be read or modified in normal
user or background debug modes.

===

I'll agree that still isn't totally clear. It does look like the "IFR" isn't accessible to your code. It determines the initial hardware trim register values. It looks like your USER CODE has to write alternate or updated values to the hardware. I think the "default" locations for this information are as detailed in the above section, but frankly you could probably store the new values anywhere convenient to you. It does look like "your user code has to update these values as you see fit" though.

If you search for "flash information row" on Freescale's site you'll find 28 references (in other product manuals). The one I looked at (MCF52259RM.pdf) is worse than the MCF51QE one, it only gives referrals in notes without any details. It might be worth looking at the other 27 manuals to see if any of them are any better.

Tom

[TomE]

The chips should be already set pretty well from the factory. You should be able to read the existing "factory trim" values from the hardware registers, and then should only need minor adjustments from those values.

[nijaju]

Thanks for the info. I didn't really think to go read the manuals for other chips but that could be handy. I've read that the chips should be already set with a good value from the factory but that never seemed to be the case. Well, that might be true for mass programming but I think my programmer wipes that all out and sets its own. Here's what I found today: 1 is relevant information but 2 is the answer I was looking for.

1) In the True-Time Simulator & Real-Time Debugger window, under CFMultilinkCyclonePro->Setup->Debug options, there's a check box for "Program trim data upon application loading" which is checked by default. With this box checked, ICSTRM is populated with values from address 0x3FF which is programmed with a chip specific value (see number 2 below). If this box is not checked, ICSTRM is initialized as 0x80 (which is consistent with what I've read in reference manuals) and the value at address 0x3FF is set to 0xFF.

2) In the Connection Manager (True-Time Simulator & Real-Time Debugger window->CFMultilinkCyclonePro->Communication), there's a check box called "Use custom trim reference frequency" which has a box to enter a value in Hz and a hyperlink next to that with the text "Click for trim details." Clicking the link takes me to a web page which says "Please check back soon for more information." I believe this page should contain that missing information I mentioned in my original post. It's been that way for months now, maybe even years? If I enter a custom trim reference frequency, this changes the value that's programmed into address 0x3FF and the initialization of ICSTRM. If I use the default trim reference value of 32768.00 Hz, I get a bus clock frequency of 4.19 MHz (for both chips), but I really want a Bus Clock frequency of 4MHz. It turns out that using the lowest custom trim reference frequency allowed, 31250.00 Hz, I get my 4 Mhz Bus Clock (for both chips). I'm sure there's some reason for this but I don't know what it is. Note that 4 Mhz / 31250 Hz = a nice round 128.

So...I've got my 4MHz clock for both chips now which makes me happy. I'd still like to know what the web page which is supposed to have trim details is supposed to tell me. Perhaps Freescale could fix this (http://www.pemicro.com/fixedlinks/trimdetails.cfm?icstype=0). I imagine it would tell me that using a 31250.00 Hz custom trim reference frequency would give me a 4MHz Bus Clock? Hopefully this information is useful to anyone else stumbling through this in the future.