Unstable ADC result

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

Unstable ADC result

跳至解决方案
3,013 次查看
Cary
Contributor I

I am using the MCF52259 micro to sample 8 channels.  The ADC results fluctuate (several hundred counts) even though the analog inputs are rock solid.  The VDD have some ripples (~25mV) and VDDA and VREFH have <5mV ripples.  So I don't think that problem lies with supply voltage.  I am using the ADC in once sequential mode with auto power down.  I re-arm the ADC every 250ms.  Any idea why the results are unstable?  Here is my ADC code:

 

void AdcInit(void) {
   MCF_ADC_CTRL1 = MCF_ADC_CTRL1_SMODE(0);      /* once sequential scan mode */
   MCF_ADC_CTRL2 = MCF_ADC_CTRL2_DIV(47);
   MCF_ADC_POWER = MCF_ADC_POWER_PUDELAY(13) | MCF_ADC_POWER_APD | MCF_ADC_POWER_PD2;
 }

void AdcTask(void) {
   for(;:smileywink: {
      MCF_ADC_CTRL1 |= MCF_ADC_CTRL1_STOP0;

      /* start conversion */
      MCF_ADC_CTRL1 &= ~MCF_ADC_CTRL1_STOP0;
      MCF_ADC_CTRL1 |= MCF_ADC_CTRL1_START0;
      
      delay for 250ms
   }
}

 

I also played around with different ADC clock values (from 10 to 63).  I found that different clock values yield different ADC results with the same input level.  Shouldn't the ADC result be independent of the clock?  I also noticed that the fluctuation worsen with higher clock frequency.

 

Any help is greatly appreciated.

标签 (1)
0 项奖励
回复
1 解答
1,961 次查看
scifi
Senior Contributor I

The signal source for the ADC should be sufficiently low-impedance in order to fully charge the ADC sampling capacitor during sampling. Sampling time depends on ADC clock, so this could explain why your results depend on ADC clock too.

If the signal is slow varying, a capactor (tens of nanofarads) at the input of the ADC should provide sufficient charge for the sampling capacitor.

By the way, the reference voltage and supply voltage should come from low-impedance sources too. This usually means sufficient number of ceramic decoupling capacitors close to MCU pins.

在原帖中查看解决方案

0 项奖励
回复
4 回复数
1,961 次查看
boogy
Contributor III

Have you measured the ADC linearity?

Try plotting voltage vs count and see if it is a straight line.

I have a similar issue and have resorted to sampling method in firmware.

I have also found that VRH pin is very sensitive to noise.

0 项奖励
回复
1,961 次查看
Cary
Contributor I

Thanks for the tip, boogy.  I am watching VRH like a hawk now.

0 项奖励
回复
1,962 次查看
scifi
Senior Contributor I

The signal source for the ADC should be sufficiently low-impedance in order to fully charge the ADC sampling capacitor during sampling. Sampling time depends on ADC clock, so this could explain why your results depend on ADC clock too.

If the signal is slow varying, a capactor (tens of nanofarads) at the input of the ADC should provide sufficient charge for the sampling capacitor.

By the way, the reference voltage and supply voltage should come from low-impedance sources too. This usually means sufficient number of ceramic decoupling capacitors close to MCU pins.

0 项奖励
回复
1,961 次查看
Cary
Contributor I

Thank you scifi.  That was it.  My signal source had too high impedance.

0 项奖励
回复