MMU Table Entry in Lauterbach Script

[vinothkumars]

Hi All,

I done the lauterbach script for t4160rdb board. I have the demo script and I workthrogh it and from this script I don't know what is MMU TLB entry.

Please, provide the detailed explanation or reference document for the following,

;MMU setup
MMU.TLB1.Set 0. 0xC0000A00 0xC0000008 0xC0000015 0x00000000 0x00000000 ;FLASH 0xC0000000--0xffffffff (1GB)
MMU.TLB1.Set 1. 0xC0000A00 0x00000000 0x00000015 0x00000000 0x00000000 ;DDR 0x00000000--0x3fffffff (1GB)
MMU.TLB1.Set 2. 0xC0000A00 0x40000000 0x40000015 0x00000000 0x00000000 ;DDR 0x40000000--0x7fffffff (1GB)
MMU.TLB1.Set 3. 0xC0000A00 0x80000000 0x80000015 0x00000000 0x00000000 ;DDR 0x80000000--0xbfffffff (1GB)

Your suggestion will be very helpful If it related to QorIq T4 series . 

Thank you for all your help ...........!

Regards, VinothS

[rweiss]

Hi,

the debugger commands are described in debugger_ppcqoriq.pdf.

You can find it in the PDF folder of your TRACE32 installation.

Best regards,

Reinhard

[vinothkumars]

Hi Reinhard,

Thank you for your reply

Thanks, VinothS

[alexander_yakov · Accepted solution]

The e6500 core uses TLB entries to map pages of real memory. Each TLB entry contains
a set of attributes which describe how the core and the system should treat core accesses
to that page.

TLB entries are not directly accessible, the core updates TLB entries through special MMU Assist (MAS) registers.

However, debugger can access TLB entries directly using debugger commands like MMU.TLB1.Set above.

For more details about MMU TLB entries, please look e6500 Core Reference Manual, Chapter 7.

https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf

For debugger commands description please refer to debugger documentation.

Have a great day,
Alexander
TIC

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[vinothkumars]

Hi Alexander,

Thank you for your quick response..

Regards, VinotS

[vinothkumars]

Hi Alexander,

I tried your suggestion. But, still I have some confusion. Will you please give detailed explanation for configure MMU TLB entry for flash and configure. Still I am struggled in that same step.

In init_rev.cmm,

;MMU setup
MMU.TLB1.Set 0. 0xC0000A00 0xC0000008 0xC0000015 0x00000000 0x00000000 ;FLASH 0xC0000000--0xffffffff (1GB)
MMU.TLB1.Set 1. 0xC0000A00 0x00000000 0x00000015 0x00000000 0x00000000 ;DDR 0x00000000--0x3fffffff (1GB)
MMU.TLB1.Set 2. 0xC0000A00 0x40000000 0x40000015 0x00000000 0x00000000 ;DDR 0x40000000--0x7fffffff (1GB)
MMU.TLB1.Set 3. 0xC0000A00 0x80000000 0x80000015 0x00000000 0x00000000 ;DDR 0x80000000--0xbfffffff (1GB)

In flash_cfi.cmm

;TLB entry for FLASH 0xC0000000--0xffffffff (caching inhibited - memory access guarded)
MMU.TLB1.Set 0. 0xC0000A00 0xC000000A 0xC0000015 0x00000000 0x0

;TLB entry for CPC-SRAM 0x10000000--0x100FFFFF 
MMU.TLB1.Set 1. 0x80000500 0x10000002 0x10000015 0x00000000 0x0

If it possible please explain anyone of the MMU  TLB entry.

And also I struggled in selection of LAW register for DDR, NOR FLASH and SRAM. If it possible please give some document to configure LAW register (It will be very helpful if t4160rdb machine)

Thank you for your help...........!

Regards, VinothS