PCIe of i.MX6 don’t work with external clock

[massohy]

Dear Community Member,

I am trying PCIe with new original board. Its PCIe is driven by external clock.  

PCIe use input clock from CLK_1N/P. Its clock is 100MHz and LVDS level.

I modified clk-imx6.c, pci-imx6.c and dts file in tune with inputting external clock in reference to this thread. i.MX6q PCIe with external clock and SATA https://community.nxp.com/thread/455537

    clocks {

        anaclk1 {

                compatible = "fixed-clock";

                reg = <0>;

                #clock-cells = <0>;

                clock-frequency = <100000000>;  /* 100MHz */

            };

    };

&pcie {

    status = "okay";

    clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,

             <&clks IMX6QDL_CLK_LVDS1_IN>,

             <&clks IMX6QDL_CLK_PCIE_REF_125M>,

             <&clks IMX6QDL_PLL6_BYPASS>,

             <&clks IMX6QDL_PLL6_BYPASS_SRC>;

    clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext", "pcie_ext_src";

    ext_osc = <1>;

};

&clks {

        assigned-clocks = <&clks IMX6QDL_PLL6_BYPASS_SRC>,

                          <&clks IMX6QDL_PLL6_BYPASS>;

        assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS1_IN>,

                                 <&clks IMX6QDL_PLL6_BYPASS_SRC>;

        assigned-clock-rates = <100000000>, <100000000>;

};

And I added this line in *.cfg file of u-boot in reference to this thread. Setting the iMX6 PCIe Clocks  https://community.nxp.com/docs/DOC-101788

DATA 4, 0x020c80e4, 0x00010501

But I encountered these messages at booting kernel.

1ffc000.pcie supply pcie-bus not found, using dummy regulator

imx6q-pcie 1ffc000.pcie: phy link never came up

imx6q-pcie 1ffc000.pcie: Failed to bring link up!

imx6q-pcie 1ffc000.pcie: failed to initialize host

imx6q-pcie: probe of 1ffc000.pcie failed with error -22

Please tell me where I should check and modify.

[massohy]

After I changed device tree like above, then CCM_ANALOG_PLL_ENET become to 0x00017000. It means PLL is down. Is it no problem because PCIe use external clock? Or should it be PLL locked and ENABLE_100M asserted?

[igorpadykov · Accepted solution]

Hi mas

seems you are right, if external clock is used, pll is not needed.

You can try to test several pcie cards for "link-up" issue, recommended to use linux

from nxp repository

linux-imx - i.MX Linux kernel 

Best regards
igor
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[massohy]

Hi igor,

I succeeded to establish PCIe connection between i.MX6 and FPGA.

I replaced pci-imx6.c to newer file. And I patched these two points.

- LOW_ACTIVE

- if (imx6_pcie->ext_osc /*&& is_imx6qp_pcie(imx6_pcie)*/) {

to pci-imx6.c.

And I activated PCIe end point unit on FPGA.

I got that those messages were also displayed at not only when driver cannot input correct clock but when PCIe EP not connected . 

Thank you for your advice.

best regards,

[massohy]

I want set CCM_ANALOG_PLL_ENET to 0x00114000. But I checked that register after kernel booted, then it was 0x00017000. What file should I change for setting that register value before initializing pci driver.