Setting the iMX6 PCIe Clocks

Document created by Brad Stewart Employee on Aug 6, 2014Last modified by Brad Stewart Employee on Sep 8, 2015
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Setting up the clocks for PCIe is a bit tricky, especially for bare-metal or if not using the Linux BSP.

The ENET PLL (PLL6) 100 MHz (SATA) PFD output MUST be enabled in order to access the registers in the PCIe IP block.


(To enable this clock, set CCM_ANALOG_PLL_ENET[ENABLE_100M (bit 20)].)


This is not well documented in the RM, but follow these steps to insure reliable performance.

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