If I use two MT48LC4M32B2 to form 64bit data, connect to the CS1 chip on the 60x BUS. B60x_ADD28 is connected to A0 of SDRAM, B60x_ADD27 is connected to A1 of BDRAM...B60x_ADD16 is connected to A12 of SDRAM, where SDA10 is connected to A10 of SDRAM, and BNKSEL is connected to BA of SDRAM. PSDMR is configured as 0xc24b36a3, OR1 is configured as 0xfe002ec0, BR1 is configured as 0xf0000041, and SIUMCR is configured as 0x0e200000. Is this correct?