In context of iMX7D.
I would like to verify: for the SW_M4P_RST, and SW_M4C_RST, does the M4P (platform) reset holds the core in reset or halted after the reset? Unlike M4C (core) reset, which resets restarts the core?
(Refreshing myself with AN5317.pdf, and this is how I think it should work using the steps in the doc... )
Also bit 0 - SW_M4C_NON_SCLR_RST (which was marked as reserved field, in rev 0 of the manual, I think, and definitely so in the AN5317) : is the only difference to the SW_M4C_RST is that it software controls when the core may come out of reset / start running again? Or is there anything else.