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IMX7 M4 caching and execution speed

Question asked by Arnout Diels on Mar 15, 2017
Latest reply on Oct 25, 2017 by TomE
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We are writing bare metal code for the M4 on the IMX7.

We noticed a huge difference in execution speed between TCM code execution, OCRAM and DDR.

A simple while loop of a = a + 1 (a being a volatile long long int) results in the following measurements (no lmem caching done)

- 24M/s loops in TCM

- 3M/s loops in OCRAM

- 0.7M/s loops in DDR


> From the reference manual, it seems that DDR can only be cached with the LMEM controller in the memory range of 0x8000_0000 until 0x801F_FFFF. Is this correct?) If so, is there an application note / info about how to avoid linux from using this memory? 


OCRAM is fast, but still a lot slower than TCM. This memory (0x2020_0000 - 0x203F_FFFF) should be able to be cached though. In order to try this we:

- Use the imx_driver code, and launch:



This has no significant effect though.

- We also tried to configure the MPU, by marking all other regions as non-cacheable, and only the OCRAM region as cacheable.. This also did not have any positive effect.


> Are we missing something here? Is there example code available that correctly uses the LMEM imx driver code to accelerate OCRAM (or any other region)?


Thanks in advance for your reply.