MX6 SoloX bare metal startup 

Document created by Yuri Muhin Employee on Jul 9, 2015Last modified by ebiz_ws_prod on Dec 13, 2017
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According to section 13.5 (Cortex-M4 Boot Requirements) of the i.MX6SX  Reference Manual :

• Cortex-A9 always boots as the primary core.

• Cortex-M4 does not have a boot ROM and at POR is not provided a clock.

• Cortex-A9 ROM is responsible for the following:

• Loading and authenticating A9 bootloader and initiating Cortex-M4
firmware as a unified image.

• Setting up Cortex-M4 initial exception table in TCRAML

• Launching the Cortex-M4 by enabling its clock.

In addition :  M4 obtains minimal initial vector table, containing

a) Initial Stack pointer

b) Reset vector

c) NMI vector

from a fixed location (zero offset) in TCM(L) after A9 enables it’s clock.


So, A9 (bootloader) is responsible for:


    Configuring M4 initial vector table  in TCM(L) ;

    Loading M4 code ;

    Configuring CSU and RDC for TrustZone (if needed)

      and A9/M4 domain separation ;

    Enabling M4 clock.


   Please look at the enclosed projects, which help to understand how to build, load

and run startup codes for both Cortex-A9 and Cortex-M4 cores of i.MX6 SoloX.


  Also note : the i.MX6 SoloX has two cores with different address mapping.

Please refer to Table 2-1 (System memory map) for Cortex-A9 core and

to Table 2-2 (CM4 memory map) for Cortex-M4 of the i.MX6 SoloX

Reference Manual. To run Cortex-M4 it is needed to fill TCM(L), that
is addressed as TCML ALIAS (from zero). The same memory is mapped

to 0x007f8000 of the Cortex-A9 (non-reflected in the Table 2-1).
Note, this area is accessible by the Cortex-A9 after M4 clock is enabled


The following resources may be helpful, when working with i.MX6 SoloX :

“How to configure Real View ICE  and RealView debugger  to work with i.MX6 SoloX”

“Integrating Processor Expert for i.MX and ARM GCC with Eclipse”

“I.MX6SX start M4 from U-Boot with QSPI flash”


"Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo "

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