CAN FD 2Mbps buad rate is not working..

[jaewoosong]

I develop ECU related CAN FD by using S32K144.

My product CAN FD baud rate requirement is 2Mbps.

CAN FD is not working in only 2Mbps.

I changed baud rate variously as 500kbps, 1Mbps, 1454kbps, 1777kbps.

But CAN FD is working well in all condition except for 2Mbps.

Below is setting of CAN FD for 2Mbps

<Processor expert of S32 Design studio>

1) PE clock source : Sys clock (40 MHz)

2) Arbitration Phase

- Propagation segment : 7

- Phase segment 1 : 6

- Phase segment 2 : 3

- Prescaler Division Factor : 3

- Resync jump width : 1

- Bitrate : 500kbps

- Sampling point : 80%

3) Data Phase

- Propagation segment : 11

- Phase segment 1 : 3

- Phase segment 2 : 3

- Prescaler Division Factor : 0

- Resync jump width : 1

- Bitrate : 2000kbps

- Sampling point : 80%

<Network Hardware Configuration of CANoe>

1) Mode : CAN FD

2) Arbitration phase

- Baud rate : 500kbps

- Sampling point : 80%

3) Data phase

- Baud rate : 2000kbps

- Sampling point : 80%

Thank you.

[PetrS · Accepted solution]

Hi Jaewoo,

do you have Transceiver Delay Compensation enabled (FDCTRL[TCDEN]=1)?

If yes, what is FDCTRL setting in fact. What is read from FDCTRL[TDCVAL]?

If not (FDCTRL[TCDEN]=0) then the bit time setting should work, I think.

What is the transceiver used on your application?

BR, Petr

[jaewoosong]

Hi Petr

Thank you for your response.

I did not use TDC function. So I enable TDCEN. And set the TDCOFF.

And then CAN FD is working well for 2Mbps. But I wonder one point.

I change the TDCOFF value variously. Error frame occurs depending on the TDC value.

Now I set the TDCOFF(5), do not occur Error frame. How do I set the proper TDCOFF value ?

void FLEXCAN_HAL_SetTDCEN(CAN_Type * base)
{
    /* Debug mode, Halt and Freeze*/
    FLEXCAN_HAL_EnterFreezeMode(base);

    /* FDRATE=1: enable Bit Rate Switch */
    /* TDCEN=1 : enable Transceiver Delay Compensation */
    /* TDCOFF=5: 5 CAN clocks offset used */
    base->FDCTRL = CAN_FDCTRL_FDRATE(1) | CAN_FDCTRL_TDCEN(1) |
                                 CAN_FDCTRL_TDCOFF(5) | CAN_FDCTRL_MBDSR0(1);

    /* De-assert Freeze Mode */
    FLEXCAN_HAL_ExitFreezeMode(base);
}

[PetrS]

Hi Jaewoo,

Theoretically the offset should be set to the middle of the data bit time, so

TDCOFF = bit_time/2 * PEclock = 225ns * 40MHz = 9.

The best approach is using a "trial and error" method to realistically find the delay value, sure it is suitable for development phase only. Set TDCOFF from 0 to max value and find the range when message is sent without error, then set TDCOFF to median of the range.

BR, Petr

[jaewoosong]

Hi Petr

I have additional question for secondary sample point.

I understood that your calculation -> (TDCOFF = bit_time/2 * PEclock = 225ns * 40MHz = 9.)

And secondary sample point is defined that measured loop delay time added to TDCOFF value

in S32K reference manual.

Finally first sample point is 80%. And what is value of secondary sample point ?

How do I calculate the secondary sample point in [%] ?

Thank you.

[PetrS]

Hi Jaewoo,

The FDCTRL[TDCVAL] specifies secondary sample point position. The value is an integer multiple of the PE clock.

Thus

SSP_delay = TDCVAL / PEclock [s]

If you want to have result in % use

SSP = SSP_delay * bitrate * 100 [%]

However you can easily get the value above 100% depending on actually measured transceiver loop delay.

BR, Petr

[jaewoosong]

Hi Petr

Thank you for response.

For example, CAN setting as below.

1) Clock : 40Mhz

2) TQ : 20 TQ

3) Sample point : 80%

4) TDCVAL : 10

5) bitrate : 2Mbps (period : 500ns)

SSP_delay = TDCVAL / PEclock [s]

              = 10 x 25ns(40Mhz)

              = 250ns

SSP = SSP_delay * bitrate * 100 [%]

        = 250ns / 500ns(2Mbps) * 100 [%]

        = 50%

Actually First smaple point is 80% (500ns x 80 / 100). So bit sample timing is 400ns.

And Secondary sample point is that First sample point + SSP_delay (650ns = 80%(400ns) + 50%(250 ns) )

Above calculation is right ?

[PetrS]

Hi Jaewoo,

Your calculation is correct except of the last one.

There is no combination of both sample points. Either regular sample point is used, if TDC is disabled, or secondary sample point is used instead, if the TDC is enabled.

The SSP must be used if the transceiver loop delay is greater than a bit time, so the MCU cannot sample the same bit that is transmitted.

BR, Petr

[jaewoosong]

Thank you for response.

[jaewoosong]

Thank you for your response.