I am doing prelayout simulation for i.MX6UL processor with DDR3L.
However in Ref. manual I can see ODT available for all address and control lines.
Also in Hyperlynx for model selection I am not able to understand for processor why address line can be configured as input. The same is shown in attached figure.
I also could not find the list of ODT's available for data lines in reference manual. However I can see them in Hyperlynx model selector. The same shown in attached image.
Let me know if I am using the correct IBIS model for CPU.