Hi Community,
Hardware:imx6q, 4G DDR3, 32G SD;
SoftWare: imx_3.0.101 (base on imx_3.0.35_4.1.0), Qt5.4
I am doing add uboot logo refer to Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and L... ,i have compared and modified different patchs all of them, and it seems work well, but it will reboot abnormally when i display a video or copy some files from u disk to board, it reboot with no log, I am very anxious for our products will soon be put into production. we need some advice.
I add attachments here.
thank you.
Hi
if reboot occurs during high intensive memory transfers, as
display a video or copy some files from u disk, this may point to
board noise and memory errors due to that noise.
It may be useful to check power lines with oscilloscope and try to run system with lower frequencies.
Just for test one can try the following experiments to determine if it is a hardware issue.
Hand solder 22uF capacitors directly under center of chip. Solder on top of the 0402 chips.
Have software Increase voltages of ARM_CAP, SOC_CAP, PU_CAP.
Also recommended to rerun ddr test.
https://community.freescale.com/docs/DOC-105652
Best regards
igor
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Hi igor,
thank you for your replay. our board runs well before i add patchs to keep logo. i just change lvds clock source from pll2 to pll5 in uboot, it seems well, i need more test.
our screen is 1920x1080, i enable split mode, so which clock source come from for lvds? pll2 or pll5, or both?
Hi igor,
i attach my patch file here.
when i use keep logo from uboot to kernel, power become larger, i have burned two boards, voltage-regulator tube has burned both of them, i think of lvds、di or ipu's clocks are not correct, makes board change the power.
in uboot:
we use ipu1 split mode, should we use both di0 and di1? is it correct the modified codes as follows:
uboot-imx/cpu/arm_cortexa8/mx6/generic.c:
before:
#ifdef LVDS_CLOCK_SRC_PLL5
/* Set ldb_di_clk clock source to PLL5 */
reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
if (di == 0) {
reg &= ~(0x7 << 9);
reg |= (0x0 << 9);
} else if (di == 1) {
reg &= ~(0x7 << 12);
reg |= (0x0 << 12);
}
writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
#else
modified:
#ifdef LVDS_CLOCK_SRC_PLL5
/* Set ldb_di_clk clock source to PLL5 */
reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
if (di == 0) {
reg &= ~(0x7 << 9);
reg |= (0x0 << 9);
#ifdef LVDS_SPLIT_MODE
reg &= ~(0x7 << 12);
reg |= (0x0 << 12);
#endif
} else if (di == 1) {
reg &= ~(0x7 << 12);
reg |= (0x0 << 12);
}
writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
#else
shoud i set di0 and di1's ldb_di_clk clock source to PLL5 in split mode.
I am nervous, my boss has been urged me.
For split mode, only one DI needs be used. For your issue, I think your hardware should check whcih power was increased?
HI,
Thank you for your reply. it is not hardware problem, it happend when i use these patchs. it is the same board. have you see the patch attached.