In my board only have sd4 look at pg1
pg1
the code such as :
configs file :
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
| #define CONFIG_MMCROOT | "/dev/mmcblk3p2" /* SDHC4 */ |
#define CONFIG_SYS_FSL_USDHC_NUM 3
| #define CONFIG_SYS_MMC_ENV_DEV | 2 /* SDHC4 */ | |
| #define CONFIG_SYS_MMC_ENV_PART | 0 | /* user partition */ |
borad .c
tatic iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD */
MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[1] = {
// {USDHC2_BASE_ADDR},
// {USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int mmc_get_env_devno(void)
{
u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
u32 dev_no;
u32 bootsel;
bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
/* If not boot from sd/mmc, use default value */
if (bootsel != 1)
return CONFIG_SYS_MMC_ENV_DEV;
/* BOOT_CFG2[3] and BOOT_CFG2[4] */
dev_no = (soc_sbmr & 0x00001800) >> 11;
/* need ubstract 1 to map to the mmc device id
* see the comments in board_mmc_init function
*/
dev_no--;
return dev_no;
}
int mmc_map_to_kernel_blk(int dev_no)
{
return dev_no + 1;
}
//#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
#define USDHC4_CD_GPIO IMX_GPIO_NR(1, 16)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
// case USDHC2_BASE_ADDR:
// ret = !gpio_get_value(USDHC2_CD_GPIO);
//break;
//case USDHC3_BASE_ADDR:
//ret = !gpio_get_value(USDHC3_CD_GPIO);
// break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
// ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int ret;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 SD4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch :smileyinfo: {
// case 0:
// imx_iomux_v3_setup_multiple_pads(
// usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
// gpio_direction_input(USDHC2_CD_GPIO);
// usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
// break;
// case 1:
// imx_iomux_v3_setup_multiple_pads(
// usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
// gpio_direction_input(USDHC3_CD_GPIO);
// usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
// break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
#else
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1
* 0x2 SD2
* 0x3 SD4
*/
switch (reg & 0x3) {
// case 0x1:
// imx_iomux_v3_setup_multiple_pads(
// usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
// usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
// usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
// gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
// break;
// case 0x2:
// imx_iomux_v3_setup_multiple_pads(
// usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
// usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
// usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
// gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
// break;
case 0x3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
}
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#endif
int check_mmc_autodetect(void)
{
char *autodetect_str = getenv("mmcautodetect");
if ((autodetect_str != NULL) &&
(strcmp(autodetect_str, "yes") == 0)) {
return 1;
}
return 0;
}
void board_late_mmc_env_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_devno();
if (!check_mmc_autodetect())
return;
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
return 0;
}
build u-boot.imx ,but i can not find sd4,as :
U-Boot 2015.04-14468-gd7d7c43-dirty (Jun 22 2016 - 15:02:33)
CPU: Freescale i.MX6Q rev1.5 at 792 MHz
CPU: Temperature 38 C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: Warning: you configured more USDHC controllers(1) then supported by the board (3)
FSL_SDHC: 0
MMC Device 2 not found
No MMC card found
Using default environment
In: serial
Out: serial
Err: serial
MMC Device 2 not found
no mmc device at slot 2
Net: FEC [PRIME]
Error: FEC address not set.
Boot from USB for mfgtools
Use default environment for mfgtools
Run bootcmd_mfg: run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};
Hit any key to stop autoboot: 0
Bad Linux ARM zImage magic!
=>
Thanks
