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Question asked by Jason Hendrix on Apr 15, 2016
Latest reply on Apr 19, 2016 by Jason Hendrix

My question is: why is PLLPGSR:CFG = 4 (an invalid value) when SYS_PLL_RAT = 3?


Hi, I'm trying to verify that my clocking is OK after a JTAG reset.  I'm having trouble with UARTs, which are driven by the platform clock, so I'm checking the platform clock configuration. 

My RCW in QSPI flash, and in the DCFG_CCSR_RCWSR1 register is 0x0608000A.  I think this is a pretty standard value for the LS1021ATWR dev board that I'm using.  Parsing this value yields a SYS_PLL_RAT of 3, for a multiplier of 3.  Now going to the PLLPGSR register in section 4.3.5 of the LS1021ARM, it says that the CFG field is based on SYS_PLL_RAT.  My system has a '4' in this CFG field.  The doc also says that valid values are 7 through 16, which is hard to reconcile with the SYS_PLL_RAT values of 2, 3, or 4.  It seems likely that I'm not understanding what these fields mean, or that there is a typo in the PLLPGSR:CFG description. Even so, why a 4 and not a 3?