AnsweredAssumed Answered

S12ZVMx12EVB PLL configuration with External crystal.

Question asked by AMEY KHATAVKAR on Jan 27, 2016
Latest reply on Feb 2, 2016 by AMEY KHATAVKAR

Hi,

 

I am using S12ZVM evaluation board (S12ZVMx12EVB), and I am trying to configure PLL clock frequency as 100Mhz so that the Bus frequency will 50HZ.

For this I have set following register value considering crystal of 4MHz-

 

     setReg16(IVBR, 0xFFFEU); 

   

    /* Disable the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the

     * internal bus clock.

     * ECLKCTL: NECLK=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

    setReg8(ECLKCTL, 0x80U);   

   

    /*  System clock initialization */

   

    /* Procedure proposed by to setup PLL and Oscillator */

    /* For OSC = 4 MHz and Bus Clock = 50MHz, That is VCOCLK = 100MHz */

   

    /* Protection of the clock configuration registers from accidental overwrite

     * CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */

    setReg8(CPMUPROT, 0x26U);            /* Disable protection of clock configuration registers */

   

    /* As we are using RTI, to do not halt RTI in staop mode we need to use Pseudo Stop Mode.

     * CPMUCLKS: PSTP=1 */

    clrReg8Bits(CPMUCLKS, 0x40U);

   

    /* System clocks are derived from PLLCLK, fbus = fPLL / 2.

     * CPMUCLKS: PLLSEL=1 */

    setReg8Bits(CPMUCLKS, 0x80U);        /* Enable the PLL to allow write to divider registers */

   

    /* PLL Clock = 100 MHz, divide by one *

     * If PLL is locked (LOCK=1),fPLL = fVCO/(POSTDIV + 1)

     * Here, fPLL = fVCO

     * CPMUPOSTDIV: ??=0,??=0,??=0,POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */

    setReg8(CPMUPOSTDIV, 0x00U);         /* Set the post divider register */

    

    /* Whenever changing PLL reference clock (REFCLK) frequency to a higher value

        * it is recommended to write CPMUSYNR = 0x00 in order to stay within specified

        * maximum frequency of the MCU

     * CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=0,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */

    setReg8(CPMUSYNR, 0x00U);            /* Set the multiplier register */

 

    /* configure PLL reference clock (REFCLK) for usage with Oscillator

     * OSC = 4MHz divide by 2 (1+1) = 2 MHz, REFCLK range 1MHz to 2 MHz (REFFRQ[1:0] = 00)

     * CPMUREFDIV: REFFRQ1=0,REFFRQ0=0,??=0,??=0,REFDIV3=0,REFDIV2=1,REFDIV1=1,REFDIV0=1 */

    setReg8(CPMUREFDIV, 0x01U);          /* Set the divider register */

 

    /* enabled oscillator clock monitor reset

     * It must be done before setting OSCE bit in CPMUOSC register

     * CPMUOSC2: ??=0,??=0,??=0,??=0,??=0,??=0,OMRE=1,OSCMOD=0 */

    setReg8(CPMUOSC2, 0x02U);            /* Configure external oscillator options */

 

    /* enable external Oscillator, switch PLL reference clock (REFCLK) to OSC

     * CPMUOSC: OSCE=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ 

    setReg8(CPMUOSC, 0x80U);             /* Enable the oscillator */

 

    /* CPMUPLL: ??=0,??=0,FM1=0,FM0=0,??=0,??=0,??=0,??=0 */

    setReg8(CPMUPLL, 0x00U);             /* Set the PLL frequency modulation */

   

    /* multiply REFCLK = 2MHz by 2*(24+1)*2MHz = 100MHz

     * VCO range 80 to 100 MHz (VCOFRQ[1:0] = 11)

       * SYNDIV = 24

     * CPMUSYNR: VCOFRQ1=1,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=1,SYNDIV3=1,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */

    setReg8(CPMUSYNR, 0xD8U);            /* Set the multiplier register */

 

    /* Check The oscillator is qualified by the PLL*/

    while(CPMUIFLG_UPOSC == 0U) {        /* Wait until the oscillator is qualified by the PLL */

    }

 

 

But with this configuration Controller getting hang/going into exception. when I tried to change and configure the fPLL bellow 60Mhz it is working fine.

Please help me to resolve this issue.

 

Regards,

Amey

Outcomes