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Appropriate termination for unused DDR3 pins on a i.MX6 dual/quad design with 32-bit bus

Question asked by Greg Lepley on Dec 10, 2015
Latest reply on Dec 10, 2015 by igorpadykov



We are looking to create a line of products that utilize i.MX6 Solo, Dual, and Quad processors. Our desire is to change as little as possible in layout between each variant of the iMX6. The Solo provides support for a 32-bit DDR3 bus and the other 32-bits are left NC according to documentation for the Solo. For the time being, we would like to keep the 32-bit bus implemented in the Dual and Quad variants as well with the option of moving to 64-bits at a later date. What are the appropriate actions to take with the unused 32 data lines on the Dual/Quad processors? Is it safe to leave them NC and floating or should we tie them high or low? We cannot find documentation that provides the appropriate design rules for this situation.


Thank you,