There are two diagrams in the reference manual, one on pg.137 (in the general clock generation section) which does not have a fractional clock divider:

and the diagram on pg.831 (in the I2S section) which does have one:

On page 832 there is also a description of how it is used:

"The MCLK fractional clock divider uses both clock edges from the input clock to

generate a divided down clock that will approximate the output frequency, but without

creating any new clock edges. Configuring FRACT and DIVIDE to the same value will

result in a divide by 1 clock, while configuring FRACT higher than DIVIDE is not

supported. The duty cycle can range from 66/33 when FRACT is set to one less than

DIVIDE down to 50/50 for integer divide ratios, and will approach 50/50 for large noninteger

divide ratios. There is no cycle to cycle jitter or duty cycle variance when the

divide ratio is an integer or half integer, otherwise the divider output will oscillate

between the two divided frequencies that are the closest integer or half integer divisors of

the divider input clock frequency. The maximum jitter is therefore equal to half the

divider input clock period, since both edges of the input clock are used in generating the

divided clock."

After some experimentation, it seems like the FRACT/DIVIDE register doesn't do anything - so guessing that the first diagram (without a MCLK divider) is what is actually there. Can someone confirm this? Or is there a way to enable the FRACT/DIVIDE functionality? This would be really useful to have - as otherwise I need to use an off chip PLL or another crystal to generate an audio clock of the right frequency.

Hi Fred,

Yes , you are right , I2S module on kl26 does not support fractional divider, we can find on here :

"The module's MCLK Divide Register (MDR) is not used to control MCLK generation." on the page 109 of RM.

So there on one side, you can config the I2S clock as you said use a dedicated oscillator for your need,

or reconfiguration the PLL.

Best Regards,

Alice

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