The use of the STOP based low power modes has been investigated for systems that have continuous UART demands (that is, there is one or more UART that can receive at "any time" and the Kinetis SW may be sending data of its own to one or more UART outputs). At the same time the general power consumption needs to be held as low as possible (eg. in a battery operated system).
The VLPS mode was identified as a potentially very good compromise since it achieves low current consumption but allows UARTs to wake the system on any detected activity.
There are a few discussions about using this mode and also some examples eg.:
however these don't actually allow a randomly operating system to achieve the requirement of optimising power by staying in a low power stop mode for as much time as possible but still responding to any data (eg. at 115200 Baud) that can occur at any time (including when moving to the low power state) without risk of loss of data.
Below are notes made during tests of the design and implementation of such a system. Initially the K, KL and KE family low power modes are compared and currents measured and then the task of achieving the operation specifically for the FRDM-K64F as test vehicle is briefly documented.
The result of the study was a system operating on the FRDM-K64F that would automatically utilise either the normal or low power STOP modes but neither corrupt UART transmissions in progress nor lose UART receptions that can wake up the processor from such a mode at any point in time (or "during" the change to the low power mode). Attached is a binary file that can be loaded to the board showing that the LED blinks and the UART command line interface responds identically in any of the modes (showing no indication that low power modes are in use). Connect to the UART0 at 115kBaud via the virtual COM connection and command low power mode changes in the "Administrator" menu (menu 4) whereby "set_lp 0" commands the standard WAIT mode, "set_lp 1" commands the normal STOP mode and "set_lp 3" commands the VLPS mode ("show_lp" shows the modes available and the one that is presently being used - WAIT is the default).
The current measured at J20 shows that that the typical 28mA current (when not utilising any low power modes at 50MHz clock) is reduced to 14.4mA in WAIT mode, to 0.8mA in STOP mode and < 200uA in VLPS mode operation strategies. [The output on J1-2 can be connected to an oscilloscope to monitor the time that the processor is in the RUN mode ('0') and in the chosen low power mode ('1')].
This mode of operation (automatically controlled by the low power task and to be extended to various other peripherals with asynchronous wakeup capability) has been added to the uTasker project and is operational on KE, KL and K devices in interrupt or DMA modes (not KE since it don't support DMA) and will be included in the next release. Pilot projects are in the test phase and users with such low power requirements are welcome to join in the pilot scheme.
===============================STOP based modes =============================================================
Basis comparison of mode when a simple project flashes and LED based on SYSTICK and controls a command line menu on a UART that allows the low power modes to be changed:
The low power mode is entered whenever there is no system activity (controlled by a low power task) and any interrupt causes the mode to be exited.
FRDM-KE06Z - normal RUN mode 40MHz 14.0mA VDD_KE06Z; with basic low power mode enabled (WAIT) 5.6mA .
With STOP mode enabled 0.4mA measured when commanded (SYSTICK and UART stop operating)
FRDM-KL02Z - normal RUN mode 48MHz 7.5mA. With basic low power mode enabled 3.4mA
With STOP mode enabled 0.2mA (SYSTICK and UART stop operating)
With VLPS mode enabled approx. 0mA (SYSTICK and UART stop operating)
FRDM-K64F - normal RUN mode 120MHz 45mA ; with basic low power mode enabled (WAIT) 26mA.
With STOP mode enabled 0.8mA. (SYSTICK and UART stop operating)
With VLPS mode enabled 0.2mA. (SYSTICK and UART stop operating)
Since some settings are preserved between resets and some registers can only be written once it is generally necessary to perform a power cycle to start testing a different mode of low power operation.
Attempt to achieve full UART operation in low power modes.
- It was found that the PLL stops in any STOP based modes. If MCG_C5_PLLSTEN0 is set in MCG_C5 the PLL continues running in "normal" STOP mode but is still stopped in VLPS.
- It is necessary to allow UART transmissions to terminate before moving to a STOP mode otherwise the transmitter freezes at the point of present transmission (since clocks are stopped). For this reason the STOP mode was blocked when a UART transmission is still in progress; this means that the system is at full power during the transmission but can then utilise STOP or VLPS, etc. without transmission corruption.
- In normal WAIT mode low power mode operation of 24mA is reduced to 2.8mA in normal STOP mode. Using a low power timer as TICK (RTC was provisonally used) further UART transmissions were possible after wake up to full-speed RUN mode, returning each time to the STOP mode after they had completed.
- In VLPS mode the PLL is always out of lock after wakeup so the system clock was 50MHz rather than the original 120MHz. Re-locking the PLL will take a little time during which the UART Baud rate will be incorrect so it may be best to not use the PLL but instead run from an input clock (as in the 50MHz external clock case). Apart from the loss of PLL clock after wakeup the VLPS mode also allowed UART transmission between VLPS/RUN modes with about 200uA current consumption measured.
The PLL relock time was measured to recover form VLPS mode on the FRDM-K64F, normally operating at 120MHz with 50MHz clock source. This was found to be around 400us and shows that recovery can effect peripheral operating frequencies between the wakeup event and full operation., In STOP mode there is no (noticeable) recovery time required if the option to not disable the PLL in normal STOP mode is used.
Tests were repeated using the 50MHz external clock as system clock (16.66MHz flash clock): WAIT mode current 14.5mA; STOP mode current 0.9mA; VLPS < 0.2mA. In this case there is however no PLL recovery time and so it is much more suitable to being woken by peripherals that must immediately be able to receive.
The final step of unrestricted UART operation with automatic low power operation was to allow UART receptions to wake the processor from VLPS. Since the UARTs are not clocked in STOP based modes the edge wakeup on the UART Rx line must be used. This requires its interrupt to be configured before entering the STOP state and using it as a single shot wakeup interrupt since an interrupt on each edge is not desired in normal operation.
It was found that UART input would now wake the processor from the STOP mode without losing an input at 115kBaud. Furthermore, no interrupts were needed to actually be handled since it could be disabled after the wakeup had occurred, before re-enabling processor interrupts.
In STOP based modes the SYSTICK is also frozen and so, to ensure that TICK operation also continued correctly, a low power timer needs to be used. Initially the RTC was used (with fixed 1s) but the low power timer is generally preferred due to much greater flexibility. For this reason an option was added to allow the low power timer to operate as TICK timer, rather than the SYSTICK, which is then left disabled.
The low power timer can be used with various clocks The first test was using the 50MHz external clock, divided by 64 to get a high accuracy 50ms TICK.
- wait mode 14.7mA
- Stop mode 1.6mA
- VLPS 0.9mA
Now the system reacted identically in the STOP based modes since the tick timer was always active but the VLPS current is higher due to the fact that the low power timer is being clocked at a fast rate.
When the low power timer was clocked by the 1kHz low power RC clock (not as accurate as crystal based but adequate for many applications) the results gave optimal VLPS current consumption with normal system behaviour at all times.
- wait mode 14.2mA
- Stop mode 0.8mA
- VLPS < 0.2mA
The result is a system that works unrestricted with regards to the UARTs and automatically moves between the Run and VLPS modes automatically, spending as much time in the VLPS mode (< 0.2mA) as possible. When UART transmission is in progress (also when using DMA) the RUN mode (about 28mA) is held until complete. When in a low power stop mode any edge on the UART reception line immediately causes a change to the RUN mode so that the reception completes and can be handled.
See the following for a discussion of PLL lock time required when exiting the VLPS mode that can be restrictive to UART (or general peripheral) operation:
Original Attachment has been moved to: uTaskerV1.4.8_FRDM_K64F_LOW_POWER_UART.bin.zip