Comparing normal STOP mode and very low power STOP mode it is possible to reduce current consumption by a factor of 10..100.
In normal STOP mode the PLL can however (optionally) continue to run and so there is no recovery time after returning to RUN mode (waiting for the PLL to lock again).
In VLPS mode the PLL is always stopped (the MCG is set back to PEE mode) so the first thing that needs to be done (when not running without PLL) is to reconfigure and wait for it to lock again so that the clock frequencies are correct again.
I am wondering about the effect of this when being woked by peripherals - like UART - where the baud rate is not correct during this period. Is the recommendation to avoid using the PLL in such cases or can this procedure be kept short enough that no disruption actually takes place?