I'm using a SABRESDB which has 64-bit DDR3 DRAM. My custom hardware will have 32-bit DDR3 DRAM.
So, I'm working through creation of my custom DCD setup (in latest uboot, this is the file board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg).
I started with the very helpful spreadsheet from https://community.freescale.com/docs/DOC-93963, and I'm now just walking through this
to make sure I understand the settings.
I see at least one case where the DDR_SEL field is set as RESERVED when it appears to me that it should be set to DDR3.
I realize that in many cases, the PAD setting is taken from the corresponding GRP register, but according to the reference manual
this DDR_SEL field of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET is not covered by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
The line (taken from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg):
DATA 4 0x020e057c 0x00020030
is for the IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, and leaves the DDR_SEL bitfield set to 00 (RESERVED0).
I cross-checked this with the older (LTIB) uboot which has the code in flash_header.S and it has this line:
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
which not only doesn't set the DDR_SEL bits, but also has a different value for the DDR_INPUT field.
The spreadsheet tool appears to match the setting that was used in flash_header.S.
Since the DRAM_RESET pin is not covered by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE setting, shouldn't its DDR_SEL bitfield be 11 (DDR3)?
Also, it seems to me that the DDR_INPUT should be 0 (CMOS)???
I've ran with both of these configurations and the system seems to work just fine; but I'd like to make sure I'm properly configuring these pins.
Can someone clarify what settings are the correct ones here?