Hi @bp1979,
There is no such thing as a silly question, just silly people that don't ask questions.
PLL2 is System PLL, and PLL3 is USB1PLL.
Therefore, when selecting PLL2 PFD2, you are selecting the clock output of the System PLL passed through its third Phase Fractional Divider (PFD2):

When selecting PLL3 PFD0, you are selecting the clock output of the USB1PLL passed through its first Phase Fractional Divider (PFD0):

And finally, when selecting PLL3 SW, you are selecting the clock output of the USB1PLL directly:

CLOCK_InitSysPfd() initializes the System PLL's PFDs, while CLOCK_InitUsb1Pfd initializes the USB1PLL's PFDs.