imx rt: Which PLL clock?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

imx rt: Which PLL clock?

Jump to solution
767 Views
bp1979
Senior Contributor I

Dear NXP,

I might have a silly question, I hope you can still help me out. I am struggling to understand which clock sources I can set for flexspi.

According to the clock tool, I can choose 4 different clock sources (SEMC, PLL2 PFD2, PLL3_SW, PLL3_PDF0)

In fsl_clock I can set the pfdFrac of a clock. E.g. with "CLOCK_InitSysPfd"

But the argument to the function is only clock_pfd_t. So I can't choose PLL2 or PLL3.

Does that mean that "SysPfd" is either PLL2 or PLL3?

And if that's the case, which one is PLL3? Usb1Pfd?

0 Kudos
Reply
1 Solution
729 Views
EdwinHz
NXP TechSupport
NXP TechSupport

Hi @bp1979,

There is no such thing as a silly question, just silly people that don't ask questions.

PLL2 is System PLL, and PLL3 is USB1PLL.

Therefore, when selecting PLL2 PFD2, you are selecting the clock output of the System PLL passed through its third Phase Fractional Divider (PFD2):

EdwinHz_0-1707343424417.png

When selecting PLL3 PFD0, you are selecting the clock output of the USB1PLL passed through its first Phase Fractional Divider (PFD0):

EdwinHz_1-1707343618882.png

And finally, when selecting PLL3 SW, you are selecting the clock output of the USB1PLL directly:

EdwinHz_2-1707343669958.png

CLOCK_InitSysPfd() initializes the System PLL's PFDs, while CLOCK_InitUsb1Pfd initializes the USB1PLL's PFDs.

 

View solution in original post

1 Reply
730 Views
EdwinHz
NXP TechSupport
NXP TechSupport

Hi @bp1979,

There is no such thing as a silly question, just silly people that don't ask questions.

PLL2 is System PLL, and PLL3 is USB1PLL.

Therefore, when selecting PLL2 PFD2, you are selecting the clock output of the System PLL passed through its third Phase Fractional Divider (PFD2):

EdwinHz_0-1707343424417.png

When selecting PLL3 PFD0, you are selecting the clock output of the USB1PLL passed through its first Phase Fractional Divider (PFD0):

EdwinHz_1-1707343618882.png

And finally, when selecting PLL3 SW, you are selecting the clock output of the USB1PLL directly:

EdwinHz_2-1707343669958.png

CLOCK_InitSysPfd() initializes the System PLL's PFDs, while CLOCK_InitUsb1Pfd initializes the USB1PLL's PFDs.