I'm working on a new feature (SPEEX echo cancellation) for my hardware that, as of right now, is not working because of what appears to be not-enough-horsepower in the '1062. Its still pretty early, so its possible (i.e. likely) I just have a problem with how I'm using the echo canceller, but it raises a general question that I'm sure has already been answered somewhere regarding optimization...
I have text and data mapped to ITCM and DTCM respectively, so does it matter how I have cache configured (MPU) for those areas? Is cache even in the picture when using TCM?
tx
Ed
已解决! 转到解答。
Hi
The tightly coupled memeries operate at core speed without wait states and are not cacheable.
Regards
Mark