SEMC SDRAM autorefresh triggered manually behaviour

[Pencioner]

I have an interesting question. Let's say i want to have more deterministic SDRAM read time in bare metal application (on RT1062), where the data is accessed quite randomly and with short reads (1-4 bytes), so i want to reduce the jitter of conflicting read with auto-refresh at same time. In the application i know sometimes that i will have enough time before next read. So i want to trigger auto refresh manually by IP command registers:

    SEMC_IPCR0 = 0x80000000;

    SEMC_IPCMD = 0xA55A000C;

and then hope that this will move the next refresh deadline so that i will have less refresh-related delays in general.

Question: does SEMC reset the refresh watchdogs/counters when this command is executed, or triggering manually is just useless and will have no positive effect?