SDRAM frequency test for 133MHZ clock

[anasnadukkandiyil]

Hi team,

Please respond it is urgent.

We are working on imxrt1176 with SDRAM test code 

Could you please confirm that event if DCD and clock_config.c and ,h are having changes for new frequency 133mHZ/166MHZ?

and run a sample code of evkmimxrt1170_semc_cm7, effective frequency will be based on settings written in

status_t BOARD_InitSEMC(void)

{

semc_config_t config;

semc_sdram_config_t sdramconfig;

uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

/* Initializes the MAC configure structure to zero. */

memset(&config, 0, sizeof(semc_config_t));

memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));

/* Initialize SEMC. */

SEMC_GetDefaultConfig(&config);

config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */

SEMC_Init(SEMC, &config);

/* Configure SDRAM. */

sdramconfig.csxPinMux = kSEMC_MUXCSX0;

sdramconfig.address = 0x80000000;

sdramconfig.memsize_kbytes = 2 * 32 * 1024; /* 64MB = 2*32*1024*1KBytes*/

sdramconfig.portSize = kSEMC_PortSize32Bit; /*two 16-bit SDRAMs make up 32-bit portsize*/

sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;

sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;

sdramconfig.casLatency = kSEMC_LatencyThree;

sdramconfig.tPrecharge2Act_Ns = 15; /* tRP 15ns */

sdramconfig.tAct2ReadWrite_Ns = 15; /* tRCD 15ns */

sdramconfig.tRefreshRecovery_Ns = 70; /* Use the maximum of the (Trfc , Txsr). */

sdramconfig.tWriteRecovery_Ns = 2; /* tWR 2ns */

sdramconfig.tCkeOff_Ns =

42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/

sdramconfig.tAct2Prechage_Ns = 40; /* tRAS 40ns */

sdramconfig.tSelfRefRecovery_Ns = 70;

sdramconfig.tRefresh2Refresh_Ns = 60;

sdramconfig.tAct2Act_Ns = 2; /* tRC/tRDD 2ns */

sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);

sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */

sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;

sdramconfig.refreshBurstLen = 1;

sdramconfig.delayChain = 2;

return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);

}

if so what will be the settings for 133MHZ and 166MHZ SDRAM frequency?

[jingpan · Accepted solution]

Hi @anasnadukkandiyil ,

DCD can set clock but BOARD_InitSEMC() can't. DCD is configured in dcd.c. When compile, it will be put in image header. The bootROM can read DCD sector and configure SEMC and clock.

BOARD_InitSEMC() can overwrite SEMC settings but not clock. The SDRAM clock is set in clock_config.c. SDRAM operation speed is same to SEMC clock root.

This picture is copy from MCUXpresso config tool. You can use it to config SDRAM clock easily.

Regards,

Jing