mscale ddr tool calibrate DQ-signal skew

[michaelschuhmac]

Hello,

we have designed two i.MX8MPlus-boards with a different LPDDR4-SDRAM layout. One layout is almost the same as the NXP-Eval-board (8MPLUSLPD4-CPU) and the other layout is optimized regarding the skew of the DQ-signals within one DQS-Groupe. I calibrated both LPDDR4-design with the imx-mscale-ddr tool and then generated the lpddr4_timing.c file. The lpddr4_timing.c files for the two different LPDDR4-SDRAM-Design are the same. I thought imx-mscale-ddr tool would calibrate the skew of the DQ-signals and the generated files are different. Is there an option in the ddr-tool I must activate?   

Best regards

Michael

[Dhruvit]

Hi @michaelschuhmac,

I hope you are doing well

It is not necessary that the changes can be seen on lpddr4_timing.c because there is some tolerance for the same.

If calibration is successful then the customer doesn't need to worry about that.

Thanks & Regards,

Dhruvit Vasavada

[michaelschuhmac]

Hi Dhruvit,

thank you very much for your support. The maximum skew of the DQ-signals within a DQS-groups is about 50ps for my first ram-design and 10ps for the second one. If I take the maximum data rate of 4GT/s one UI is 250ps. That means the skew of the first ram-design equals 20% of the UI and the skew of the second design 4% of the UI. Does the DDR_PHY of the i.MX8MPlus has the ability to compensate this skew? If that feature exists, does the mscale ddr tool calibrate this skew?

Best regards

Michael

[Dhruvit]

Hi @michaelschuhmac,

I hope you are doing well.

The calibration is performed during every boot on the mScale devices therefore, the timing file itself does not contain any static calibration values and if two designs are the same (memory device, data signals mapping), then the timing file will be the same for both.

The reason why the DDR tool does not allow to generation of the timing file prior calibration is to prevent generation of invalid timing files with incorrect configurations that do not result in a successful calibration.

Thanks & Regards,
Dhruvit Vasavada

[michaelschuhmac]

Hi Dhruvit,

thank you very much for the detailed information. You helped me a lot to understand ddr-ram calibration. There is only one last point I would like to ask you. Is there a skew calibration for each Databit in a DQS-Group? The reason for me question is that I worder if the length match of each DQ line within a DQS-Grupe must be very precise (e.g. 2ps), or if some length differences (e.g. 50ps) are compensated by calibration.

Thanks & Regards,

Michael Schuhmacher

[Dhruvit]

Hi @michaelschuhmac,

I hope you are doing well.

Please accept my apologies for the delayed response.

Yes, Each DQ line is individually calibrated to compensate for the skew for both the read and write scenarios. In the Hardware Developer's Guide, for the PCB design, we allow a max skew of +/- 50 ps wrt to DQS for the DQ signals:

Thanks & Regards,
Dhruvit Vasavada