lcdif_pix_clk_enable

[rajkumarmadhani]

In my u-boot code  working on LCD . lcdif_pix_clk is not running .

these are clock controlling registers.

Anything  am i missing in clock configuration  ?

	/* LCDIF AXI clk from PFD_400M, set to 396/2 = 198MHz */
	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
	reg &= ~0x7C000;
	reg |= (0x1 << 16) | (1 << 14);	//reg = 0x00014000
	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);

	/* LCDIF AXI clk enable */
	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
	reg |= 0x00C0;
	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);

	/* LCDIF PIX clk from PFD_540M, set to 540/4/5 = 27MHz */
	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
	reg &= ~0x0FFF;
	reg |= (0x5 << 6) | (1 << 5);
	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR2);

	/* POST DIVIDET for lcdif pix clk */
	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
	reg &= ~0x00700000;
	reg |= (0x5 << 20);
	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR1);

	/* LCDIF PIX clk enable */
	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
	reg |= 0x03C0;
	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);

[igorpadykov]

Hi Rajkumar

also one needs to set correct iomux settings for clk pin and

initialize eLCDIF (perform SFTRST,CLKGATE), please check

sect.21.4.5 Initializing the eLCDIF, 21.5 Behavior During Reset,

IMX6SLRM ,  eLCDIF examples in i.MX 6Series Platform SDK

Bare-metal SDK.

Best regards

chip

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[shefft]

2

Hi, a follow up question as I'm also trying to use the LCDIF.  The terminology is not consistent in the manual for the imx6 SDL.  There is some mention of the LCDIF (not the eLCDIF) but in conjunction with the PXP.  Are they one and same?  In other words, to generate the lcdif_clk do I need to set up the PXP registers?

[igorpadykov]

Hi Tyler

yes LCDIF and eLCDIF is the same.

Regarding settings for eLCDIF I think

i.MX 6Series Platform SDK is best option.

Best regards

igor

[shefft]

1

We were able to resolve the issue by returning to using IPU1 instead.

[shefft]

2

To clarify, I'm using a Solo.  Do you have a dev guide that covers all the needed LCDIF settings?  The only relevant registers I can find are:

CSCDR2

CSCDR3

CCOSR?

CCGR3

pads:

   NEW_PAD_CTRL(MX6PAD(DI0_DISP_CLK__LCDIF_CLK), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DI0_PIN15__LCDIF_ENABLE), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DI0_PIN2__LCDIF_HSYNC), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DI0_PIN3__LCDIF_VSYNC), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DISP0_DAT0__LCDIF_DAT_0), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DISP0_DAT1__LCDIF_DAT_1), DISP_PAD_CTRL),

   NEW_PAD_CTRL(MX6PAD(DISP0_DAT2__LCDIF_DAT_2), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT3__LCDIF_DAT_3), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT4__LCDIF_DAT_4), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT5__LCDIF_DAT_5), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT6__LCDIF_DAT_6), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT7__LCDIF_DAT_7), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT8__LCDIF_DAT_8), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT9__LCDIF_DAT_9), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT10__LCDIF_DAT_10), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT11__LCDIF_DAT_11), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT12__LCDIF_DAT_12), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT13__LCDIF_DAT_13), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT14__LCDIF_DAT_14), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT15__LCDIF_DAT_15), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT16__LCDIF_DAT_16), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT17__LCDIF_DAT_17), DISP_PAD_CTRL),

    NEW_PAD_CTRL(MX6PAD(DISP0_DAT18__LCDIF_DAT_18), DISP_PAD_CTRL),