Hi,
We're using imx8ulp in "flash_singleboot_m33"mode with:
m33 firmware is based on MCUXpresso SDK 2.16.000 MIMXRT700 (https://github.com/nxp-mcuxpresso/mcux-sdk commit 021190013e4d)
uboot 2023.04 based on lf-6.1.55-2.2.2
upower firmware-upower-1.3.0
ele firmware-ele-imx-0.1.1
To ensure we're booting in a clean state we're checking `CMC_RTD->SRS` in the m33 firmware and force a reset through PMIC (write 0x14 (Cold reset) to reg 9 (SW_RST))
This has been working well, e.g. when a software watchdog hits we notice this, (log a message) and trigger a cold reset to get in clean state.
However, with some SD cards (but not all the time...), the first boot fails with CMC_RTD->SRS = 0x40000030
According to the enums I found it means these bits:
#define CMC_SRS_WARM_MASK (0x10U)
/*! WARM - Warm Reset
* 0b1..Reset generated by Warm Reset source.
*/
#define CMC_SRS_FATAL_MASK (0x20U)
/*! FATAL - Fatal Reset
* 0b1..Reset was generated by a fatal reset source.
*/
#define CMC_SRS_SRR_MASK (0x40000000U)
/*! SRR - Secure enclave Reset Request
* 0b1..Reset generated by SRR.
*/
When this happens, triggering a cold reset will reset, but it'll immediately trigger a new reset by SRR afterwards, making the soc reset endlessly.
For now I've added a check on the SRR bit and just skip triggering a cold reset in this case, which works, but I'd like to know why this reset happens in the first place as it seems dependent on hardware (doesn't happen with all SD cards, stops happening even with the same SD card if I rewrite the same firmware(!), doesn't happen on all of our boards even with a SD card that reproduces the issue reliably on one board...)
So:
- Is it possible to get more information other than that single bit? Does the reset leave some other registers we could dump? Given it's security related I doubt there is a fault handler we could catch a handler before reset like hardfault...
- If you (anyone) have any idea what this could be we'd be interested
Thank you,
Dominique