imx8mq - configure 4gb memory

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imx8mq - configure 4gb memory

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wenyong
Contributor I

Dear Nxp engineers, 

 

We have a design based on imx8mq with 3GB DDR - it's working fine. 

Now we upgrade it to 4gb memory. 

I have been following this link to apply the patch. 

https://community.nxp.com/t5/i-MX-Processors/LGE-CTO-booting-failure-with-4G-DRAM-with-OPTE/m-p/1223...

 

In this link if apply patch and disable OP-TEE, according to the discussion in the link, it should work. But my board would still stuck in "Starting Linux..."

Could you help to suggest the proper way to configure 4gb ddr?

 

This is my patch:

 

@@ -18,15 +18,12 @@
};

firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
};

memory@40000000 {
device_type = "memory";
- reg = <0x00000000 0x40000000 0 0xc0000000>;
+ reg = <0x0 0x40000000 0 0xc0000000>,
+ <0x1 0x00000000 0 0x40000000>;
};

pcie0_refclk: pcie0-refclk {
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 08bcb399b1f..0f51fb6ceef 100644
--- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig
@@ -163,10 +163,11 @@ CONFIG_SHA384=y
CONFIG_EFI_VAR_BUF_SIZE=139264
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_AUTHENTICATE=y
-CONFIG_OPTEE=y
+CONFIG_OPTEE=n
CONFIG_CMD_OPTEE_RPMB=y
CONFIG_EFI_MM_COMM_TEE=y
CONFIG_TEE=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_NR_DRAM_BANKS=2
\ No newline at end of file
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 567e120e276..70b44999b6d 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -177,6 +177,8 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x40000000 /* */

#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR

 

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pengyong_zhang
NXP Employee
NXP Employee

Hi @wenyong 

You can use our DDR Config Tool configuration the ddr MT53E1G32D2FW parameters, Then the tool will generate the new timing.c file which you can use it compile the new uboot flash.bin file to boot your board.

https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-developm...

B.R

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pengyong_zhang
NXP Employee
NXP Employee

Hi @wenyong 

You can use our DDR Config Tool configuration the ddr MT53E1G32D2FW parameters, Then the tool will generate the new timing.c file which you can use it compile the new uboot flash.bin file to boot your board.

https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-developm...

B.R

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pengyong_zhang
NXP Employee
NXP Employee

Hi @wenyong 

OK, this can support 4GB DRAM, Please share your DDR datasheet and schematic file. I will help you configurate the DDR parameters.

B.R

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wenyong
Contributor I
Thanks Pengyong, this issue is resolved by useing ddr tool to generate new timing file
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wenyong
Contributor I

Hi PengYong

 

4GB DDR4 RAM PN#: Micron MT53E1G32D2FW-046 IT:B

Same schematic and layout as the evaluation board (MCIMX8M-EVKB)

 

Thanks,

Wenyong

 

 

 

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1,079 Views
pengyong_zhang
NXP Employee
NXP Employee

Hi @wenyong 

What is your i.MX8MQ SOC Part number? Because only Quad- A53 can support 4GB DRAM.

B.R

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1,000 Views
wenyong
Contributor I

Hi pengyong, 

 

We are using PN# MIMX8MQ6CVAHZAB

 

Thanks,

Wenyong

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968 Views
wenyong
Contributor I

Hi @pengyong_zhang , 

 

We use MIMX8MQ6CVAHZAB.

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