Is there an access frequency limit for the flexspi interface of imx8mp? Now I am using 8-wire connection to FPGA, and I am doing uninterrupted read access to the same address (cache is not enabled, which means that every read access can trigger the cs signal to be valid), most of the time it is good, but sometimes I found out by monitoring that the cs signal will not be triggered for a very long time (40~50ms), which leads to the read value is especially different from the normal one, what could be the reason for this?
ps: flexspi default clock is 80Mhz.
