imx8mp additional ethernet through spi with encx24j600

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imx8mp additional ethernet through spi with encx24j600

920 Views
Savo
Contributor II

The board arch/arm64/boot/dts/freescale/imx8mp.dtsi value is

ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};

The main value is arch/arm64/boot/dts/congatec/imx8mp-cgtsx8p.dts

&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "disabled";

flash1: w25q64fw@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <500000>;
};
};


How can I add the section regarding encx24j600 to be controlled through spi.

In forums I could figure out a solution, but what about the pinout, interrupts? can be a valid solution this one? why was previously disabled?

 

./workspace/sources/linux-congatec-sx8p/arch/arm64/boot/dts/congatec/imx8mp-cgtsx8p.dts

&ecspi2 {

        #address-cells = <1>;

        #size-cells = <0>;

        fsl,spi-num-chipselects = <1>;

        pinctrl-names = "default","sleep";

        pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;

        pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;

        cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;

        status = "okay";
       encx24j600: eth3@0 {
            compatible = "microchip,encx24j600";
             status = "okay";
             reg = <0>;
             spi-max-frequency = <10000000>;
       #interrupt-parent = <&gpio0>;
       #interrupts = <54 8>;
       };

 

        flash1: w25q64fw@0 {

                reg = <0>;

                #address-cells = <1>;

                #size-cells = <1>;

                compatible = "jedec,spi-nor";

                spi-max-frequency = <500000>;

        };

};

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Savo
Contributor II

, I managed to load the driver.

I am using a spi ethernet chip. We would like to use the selector to use both ecspi as ethernets, but could manage only to use one, on position 0

This is my current config. I don’t know if you can see what’s wrong with it

 

&ecspi2 {
        #address-cells = <1>;
        #size-cells = <0>;
        fsl,spi-num-chipselects = <2>;
        pinctrl-names = "default","sleep";
        pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
        pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;
        cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
        status = "okay";

        ethphy2: ethernet@0 {
                compatible = "microchip,encx24j600";
                #address-cells = <1>;
                #size-cells = <1>;
                status="okay";
                reg = <0>;
                spi-max-frequency = <12000000>;
                interrupt-parent = <&gpio1>;
                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
        };


        ethphy3: ethernet@1 {
                compatible = "microchip,encx24j600";
                #address-cells = <1>;
                #size-cells = <1>;
                status="okay";
                reg = <1>;
                spi-max-frequency = <12000000>;
                interrupt-parent = <&gpio1>;
                interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
        };
};

 

Dmesg:

[ 5.697091] spi_imx 30830000.spi: can't get the TX DMA channel, error -517!
[ 5.711578] spi_imx 30830000.spi: registered master spi1
[ 5.712090] spi spi1.0: spi_imx_setup: mode 0, 8 bpw, 12000000 hz
[ 5.712112] spi spi1.0: setup mode 0, 8 bits/w, 12000000 Hz max --> 0
[ 5.714479] spi_imx 30830000.spi: registered child spi1.0
[ 5.714520] spi spi1.1: spi_imx_setup: mode 0, 8 bpw, 12000000 hz
[ 5.714529] spi spi1.1: setup mode 0, 8 bits/w, 12000000 Hz max --> 0
[ 5.715566] imx-sdma 30bd0000.dma-controller: firmware found.
[ 5.718532] spi_imx 30830000.spi: registered child spi1.1
[ 5.721625] imx-sdma 30bd0000.dma-controller: loaded firmware 4.6
[ 5.726910] imx-sdma 30e10000.dma-controller: firmware found.

[ 6.008094] encx24j600 spi1.0 eth2: Silicon rev ID: 0x01
[ 6.019088] encx24j600 spi1.0 eth2: MAC address 80:1f:12:12:69:1a
[ 6.027393] encx24j600 spi1.1 (unnamed net_device) (uninitialized): encx24j600: Chip is not detected
[ 6.036661] encx24j600: probe of spi1.1 failed with error -5
#ethtool eth2
Settings for eth2:
Supported ports: [ TP ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Supported pause frame use: No
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: Not reported
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
Port: Twisted Pair
PHYAD: 0
Transceiver: internal
MDI-X: Unknown
Current message level: 0x00000007 (7)
drv probe link

 

Should I add an additional chip select line to the configuration? I could find only a SS0 in the datasheet, it's like it's not possible to add a second device?

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @Savo 

The defalult ecspi support 4 slave devices.If you don't add 'num-cs' in device tree node, the num_chipselect will be 3, this is enough. 'fsl,spi-num-chipselects' is Obsolete properties.

	/*
	 * Get number of chip selects from device properties. This can be
	 * coming from device tree or boardfiles, if it is not defined,
	 * a default value of 3 chip selects will be used, as all the legacy
	 * board files have <= 3 chip selects.
	 */
	if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
		controller->num_chipselect = val;
	else
		controller->num_chipselect = 3;

 

Try to add like this:

&ecspi2 {
        #address-cells = <1>;
        #size-cells = <0>;
        fsl,spi-num-chipselects = <2>;
        pinctrl-names = "default","sleep";
        pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
        pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;
        cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,<&gpioX X GPIO_ACTIVE_LOW>;
        status = "okay";

        ethphy2: ethernet@0 {
                compatible = "microchip,encx24j600";
                #address-cells = <1>;
                #size-cells = <1>;
                status="okay";
                reg = <0>; //cs-gpio[0]
                spi-max-frequency = <12000000>;
                interrupt-parent = <&gpio1>;
                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
        };


        ethphy3: ethernet@1 {
                compatible = "microchip,encx24j600";
                #address-cells = <1>;
                #size-cells = <1>;
                status="okay";
                reg = <1>; //cs-gpio[1]
                spi-max-frequency = <12000000>;
                interrupt-parent = <&gpio1>;
                interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
        };
};

 

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748 Views
Savo
Contributor II

OK, Thanks. But what should I add for 

&gpioX X GPIO_ACTIVE_LOW

For chip select 0 is present MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13

But for chip select 1 there is no SS1 connection on the imx8mp

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

There is no relationship between ss and cs pin, the cs pin is common gpio, you can choose any unused gpio.

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Savo
Contributor II

Hello,

So yes I have the gpio multiplexed. I  made it to work, but still I don't get the interrupt from eth3. Setup:

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio6 6 GPIO_ACTIVE_LOW>;
	status = "okay";

	ethphy2: ethernet@0 {
		compatible = "microchip,encx24j600";
		#address-cells = <1>;
		#size-cells = <1>;
		status="okay";
		reg = <0>;
		spi-max-frequency = <12000000>;
		interrupt-parent = <&gpio2>;
		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
	};

	ethphy3: ethernet@1 {
		compatible = "microchip,encx24j600";
		#address-cells = <1>;
		#size-cells = <1>;
		status="okay";
		reg = <1>;
		spi-max-frequency = <12000000>;
		interrupt-parent = <&gpio2>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
	};
};
...
	pinctrl_ecspi2_cs: ecspi2cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c0
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x41
		>;
	};
...
&i2c5 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5>;
	status = "okay";

	gpio6: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

	};

	m41t62: rtc@68 {
		compatible = "st,m41t62";
		reg = <0x68>;
	};
};

 What's wrong here?  I added MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 but it's kind of useless (won't change the behaviourÇ) that is also used in pinctrl_csi0_rst

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

  I added MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 but it's kind of useless (won't change the behaviourÇ) that is also used in pinctrl_csi0_rst

-->Comment that line in pinctrl_csi0_rst, make sure there is only one device uses GPIO1_IO06 PAD.

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

If you enable the ecspi2 , you need check if there is other pinctrl node which is using same pad. 

For encx24j600 driver in kernel , there is no code to parse interrupt node or pinout. So i think the dts node you add is enough. Please check compatible in drivers/net/ethernet/microchip/encx24j600.c

static const struct spi_device_id encx24j600_spi_id_table[] = {
	{ .name = "encx24j600" },
	{ /* sentinel */ }
};

 

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Savo
Contributor II

There is a bug in the processor, as mentioned here? https://www.marcusfolkesson.se/blog/bug-in-imx8mp-ecspi-module/
What should I do to have this ecspi2 enabled then?
Dmesg:
[ 0.000000] GICv3: 160 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 1.176005] nxp-fspi 30bb0000.spi: registered master spi0
[ 1.176039] spi spi0.0: setup mode 0, 8 bits/w, 80000000 Hz max --> 0
...
[ 1.806804] gpio-138 (ecspi2-sclk-sleep): hogged as input
[ 1.812223] gpio-139 (ecspi2-mosi-sleep): hogged as input
[ 1.817636] gpio-140 (ecspi2-miso-sleep): hogged as input
Configuration enabled:

CONFIG_REGMAP_SPI=y

CONFIG_MTD_SPI_NOR=y

CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y

CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y

CONFIG_SPI=y

CONFIG_SPI_DEBUG=y

CONFIG_SPI_MASTER=y

CONFIG_SPI_MEM=y

CONFIG_SPI_BITBANG=y

CONFIG_SPI_CADENCE_QUADSPI=y

CONFIG_SPI_DW_DMA=y

CONFIG_SPI_FSL_LPSPI=y

CONFIG_SPI_FSL_QUADSPI=y

CONFIG_SPI_NXP_FLEXSPI=y

CONFIG_SPI_IMX=y

CONFIG_SPI_FSL_LIB=y

CONFIG_SPI_FSL_SPI=y

CONFIG_SPI_FSL_DSPI=y

CONFIG_SPI_PL022=y

CONFIG_SPI_ROCKCHIP=y

CONFIG_SPI_SPIDEV=y

CONFIG_SPI_SLAVE=y

CONFIG_SPI_SLAVE_TIME=y

CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y

CONFIG_SPI_DYNAMIC=y

CONFIG_MMC_SPI=y

CONFIG_RTC_I2C_AND_SPI=y

CONFIG_CROS_EC_SPI=y

CONFIG_COMMON_CLK_FSL_FLEXSPI=y

CONFIG_FXAS21002C_SPI=y

CONFIG_IIO_ST_LSM6DSX_SPI=y


My .dts:
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <2>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
pinctrl-1 = <&pinctrl_ecspi2_sleep &pinctrl_ecspi2_cs_sleep>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okey";

ethphy2: ethernet-phy@0 {
compatible = "microchip,encx24j600";
status = "okay";
reg = <0>;
spi-max-frequency = <10000000>;
};
ethphy3: ethernet-phy@1 {
compatible = "microchip,encx24j600";
status = "okay";
reg = <1>;
spi-max-frequency = <10000000>;
};

};

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

1. The node status should be okay

2. The ecspi2 node in imx8mp-evk.dts from NXP are below which can work.

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev1: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <500000>;
	};
};

 3. Why your dts disable ecspi2 in dts? This means there is other node uses same iomux pad(pinctrl node or cs pin), so the dts disable ecspi2. 

4.Why you can't see ecspi2 in log? Because other device is occupying hardware resources like iomux, so the ecspi2 can't be probed.

5.You should check the pinctrl node or cs pin mux.

6. The conclusion is that the core dts is not from NXP(only dtsi from NXP), we can't know why ecspi2 in your dts is disabled. Because the vendor may change reference design from EVK and also change dts which is different from imx8mp-evk.dts.

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Savo
Contributor II

Hello, it's not enough, I don't see anything from dmesg

ecspi2 is not in the list of aliases in arch/arm64/boot/dts/freescale/imx8mp.dtsi

Should i add it there in order to make it work?

Also, how the additional Ethernets should be added in the device tree?

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