how to config the gpio default power on state by edit imximage.cfg in the uboot code

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how to config the gpio default power on state by edit imximage.cfg in the uboot code

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bigjiong
Contributor II

HI all:

    I am using the M6Y2C-512F4GLI-T SOM board, the link is https://www.zlg.cn/index.php/ipc/ipc/product/id/238.html

    I use the MX6_PAD_SD1_CMD as GPIO2_IO16  (output use, low level default)

            and MX6_PAD_SD1_DATA0 as GPIO2_IO18  (output use, low level default)

    I found that when the mpu (power on) or (reset), this two pin output the high level.

    I want them output the low level by default,

         so I edit the int board_init(void) function,

              add the function:

                                     1) gpio_request()

                                     2) gpio_direction_output()

              it work fine, However, there is still a two-second delay from system power-on or reboot.

              In other words, there will be a high level output for two seconds.

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *  Addr-type register length (1,2 or 4 bytes)
 *  Address   absolute address of the register
 *  value     value to be stored in the register
 */
    
    This is part of the description in the imximage.cfg file.
    So I want to modify this file, And add something like this type:
 
    
DATA 4 Address(MUX_CTL_PAD_SD1_CMD_ADDRESS) value(MUX_CTL_PAD_SD1_CMD_VALUE)
 
AND I have already get the register value generate by the software which named Config_Tools_for_i.MX_v14_x64.exe
 
this is the register value:
 
#define BOARD_INITPINS_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_VALUE                      0x00000015   /*!< Register name: IOMUXC_SW_MUX_CTL_PAD_SD1_CMD */
#define BOARD_INITPINS_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_VALUE                      0x000010B0   /*!< Register name: IOMUXC_SW_PAD_CTL_PAD_SD1_CMD */
 
Can anyone tell me how to get the absolute address of the register or where to.
 

Thanks.

 

      

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AldoG
NXP TechSupport
NXP TechSupport

Hello,

You may find these registers in the processor reference manual, which is the i.MX6ULL.

32.6.95 SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
Address: 20E_0000h base + 1BCh offset = 20E_01BCh

32.6.241 SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
Address: 20E_0000h base + 448h offset = 20E_0448h

Saludos,
Aldo.

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AldoG
NXP TechSupport
NXP TechSupport

Hello,

You may find these registers in the processor reference manual, which is the i.MX6ULL.

32.6.95 SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
Address: 20E_0000h base + 1BCh offset = 20E_01BCh

32.6.241 SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
Address: 20E_0000h base + 448h offset = 20E_0448h

Saludos,
Aldo.

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bigjiong
Contributor II

Thanks for your reply @AldoG!

I have add this code to the imximage.cfg:

 

DATA 4 0x020E01BC 0x00000005
DATA 4 0x020E0448 0x000010B0
 
but there still have a high level output for two seconds 
It seems that there should be other instructions interfering with the operation.
 
and I have try to add the code to the plugin.S file as below.
 
.macro imx6_qos_setting
    ldr r0, =0x020E0000
    ldr r1, =0x00000005
    str r1, [r0, #0x1BC]
    ldr r1, =0x000030B0
    str r1, [r0, #0x448]
.endm
 
The above code is called in mx6_plugin.S, like this:
 
plugin_start:

    push    {r0-r4, lr}

    imx6_ddr_setting
    imx6_clock_gating
    imx6_qos_setting   /* <----   the code Call place */
 
Some code related to SD1 peripheral initialization may need to be commented out.
 
I will try to find out them.
 
because of The file type (.cfg and .S) is not supported to upload, I have compress those files (imximage.cfg and plugin.S) to a single .zip file.
 
Saludos,
bigjiong.
 
 
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bigjiong
Contributor II

I have add this code to the imximage.cfg, but there still have a high level output for two seconds.

 

DATA 4 0x020E01BC 0x00000005
DATA 4 0x020E01C4 0x00000005
DATA 4 0x020E0448 0x000010B0
DATA 4 0x020E0450 0x000010B0
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