Dear all,
I'm using following kind of Kernel ver. with i.MX6DL.
https://github.com/Freescale/linux-fslc/tree/4.14-1.0.x-imx
I'm facing SPI communication problem.
At the first packet of SPI communication, SPI_CLK become High↑ after CS becomes Low ↓.
That's why the MSB bit always becomes "1".
Send data "14 00 00 10 FF" -> 0b1 + 0x14 + 0x00 + ... -> Receive data "8A 00 00 08 7F"
With another CS device , we can see same phenomenon for the first packet.
Send data "00 00 xx" -> 0b1 + 0x00 + 0x00 -> Receive data "80 00 xx"
For the same device, there is no problem from 2nd packet as long as I checked.
But I don't know the root cause of this phenomenon, and when this problem happen.
In my environment, there is no EVK board, so this problem can be seen only with my own board with SPI1_cs1, cs2, cs3, SPI2_cs2.
Is there any way to avoid this problem?
Best regards,
Hi igorpadykov,
We found that this issue happen with SPI Mode3.
If I changed the setting from Mode3 to Mode0, CLK and data are no problem.
And I tried adding 50us delay as Théo mentioned at i.MX6 ecspi race condition with CPOL=1 and CS GPIO
/* CTRL register always go first to bring out controller from reset */
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
udelay(50);
reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
if (spi->mode & SPI_LOOP)
reg |= MX51_ECSPI_TESTREG_LBC;
else
reg &= ~MX51_ECSPI_TESTREG_LBC;
writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
But it does not have good effect for my case. (Our speed is 3MHz.)
This slave device can used only with SPI Mode 3, so I cannot change Mode.
At least we would like to know if this issue happen only for the first packet or not.
If someone knows that this is a known issue, please let us know.
Best regards,
Nanao Akimichi.
