Hi,
I get stuck when the u-boot is suppose to start the kernel. It is always saying bad CRC. I tried 3 different kernels, one from ltib, one from buildroot and one from timesys. I am pretty sure there is at least one good CRC kernel. Do you have something on this that I can look onto? I am pretty clueless on this.
Thank you!
CPU: Freescale i.MX6SOLO rev1.1 at 792 MHz
Reset cause: POR
Board: Wandboard
DRAM: 512 MiB
MMC: MMC XAVIER: XAVIER: Setup sdhc 1.
XAVIER: End setup.
FSL_SDHC: 0
MMC finished
In: serial
Out: serial
Err: serial
Net: Board Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> fatload mmc 0 0x10008000 uImage
XAVIER: Get mmc cd 1.
XAVIER: RET: 1
reading uImage
2623120 bytes read in 153 ms (16.3 MiB/s)
=> bootm 0x10008000
## Booting kernel from Legacy Image at 10008000 ...
Image Name: Linux-3.0.35-ts-armv7l
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2623056 Bytes = 2.5 MiB
Load Address: 10008000
Entry Point: 10008000
Verifying Checksum ... Bad Data CRC
ERROR: can't get kernel image!
Solved! Go to Solution.
I found out the problem. It was only a missing define in the bootloader. I had to add the line:
#define BOOTZ
To have CRC correct.
Thank you Fabio for all your help!
Your kernel has a wrong loadaddr. For mx6solo you should build your kernel like:
make -j4 uImage LOADADDR=0x800080000
Regards,
Fabio Estevam
Thank you Fabio for the quick answer.
Unfortunately, it does not seems to correct the problem. I used LOADADDR=0x80008000. Is this correct, just wondering because the address you gave me is 9bytes long instead of 8?
If this is ok, could it be a problem coming from the bootloader itself?
Here is the error with the kernel at 0x80008000. I used the last kernel in the freesclae imx6 repository. Thank you again:
U-Boot 2014.04-rc3-00014-g04d2f0a-dirty (Apr 11 2014 - 16:58:29)
CPU: Freescale i.MX6SOLO rev1.1 at 792 MHz
Reset cause: POR
Board: Wandboard
DRAM: 512 MiB
MMC: MMC XAVIER: XAVIER: Setup sdhc 1.
XAVIER: End setup.
FSL_SDHC: 0
MMC finished
In: serial
Out: serial
Err: serial
Net: Board Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> fatload mmc 0 10800000 uImage
XAVIER: Get mmc cd 1.
XAVIER: RET: 1
reading uImage
3840580 bytes read in 205 ms (17.9 MiB/s)
=> bootm 10800000
## Booting kernel from Legacy Image at 10800000 ...
Image Name: Linux-3.0.35-03053-g8d2b169
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3840516 Bytes = 3.7 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... Bad Data CRC
ERROR: can't get kernel image!
=>
I see that you are doing
fatload mmc 0 10800000 uImage
Should be 80800000 instead.
and also:
bootm 10800000, should be 80800000 instead.
Oops, sorry.
The 80000000 addresses are for mx6solo-lite, not mx6solo.
So the ranges you are passing are fine.
Is this a custom board? Could be related to DDR configuration?
It is possible it can come from the DDR configuration. We have a custom board based on the wandboard. We are using lpddr2 instead of ddr3 I checked on the u-boot config file and got this on the RAM:
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
As I understand, the memory range is 0x10000000 to 0x60000000 (in the wandboard solo and our board, there is 512mb RAM).
For the u-boot, I used the last u-boot in the denx repository and then configured it to use lpddr2. The wandboard is using the same configuration as the nitrogen6x for the RAM so I modified the cfg file of the nitrogen6x.
I used the lpddr2 ddr aid script v0.03 to help me. I modified the cpu clock speed to lower it to 800 and modified MMC0_MDMISC because it was S2 by default in the script but our RAM is S4.
I was able to properly start the console and I have done several write/read tests on the ram and it worked well. I also use the DDR stress test on the OTG and it passed the test without getting stuck.
Do you know where I could check to see what could be the problem?
Thank you.
Here is the final result of the lpddr2 config:
//Difference - pre_periph_clk_sel est a 10 pour eux, nous
DATA 4 0x020c4018 0x00860324 //Xavier - try to 307Mhz //DDR clk to 400MHz // nous - 0x00060324 // test 307mhz 0x000A0324
//CCM_CACRR - arm clock
//============================================================================
// IOMUX
//============================================================================
//DDR IO TYPE:
DATA 4 0x020e0774 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE (LPDDR2) // eux - 0x000C0000 (DDR3)
DATA 4 0x020e0754 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE //eux - 0x00000000
//CLOCK:
DATA 4 0x020e04ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 //eux - 0x00020030 - CMOS inout vs differential mode
DATA 4 0x020e04b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 //eux - 0x00020030 - CMOS inout vs
//ADDRESS:
DATA 4 0x020e0464 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS //eux - 0x00020030 - CMOS inout vs
DATA 4 0x020e0490 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS //eux - 0x00020030 - CMOS inout vs
DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS //eux - 0x00000030
//Control:
DATA 4 0x020e0494 0x00020000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET //eux - 0x00020030 - CMOS inout vs // nous - 0x00000030, mettre a 0 car pin disabled donc Hi Z
DATA 4 0x020e04a0 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS //eux - 0x00000000
DATA 4 0x020e04b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 //eux - 0x00003030
DATA 4 0x020e04b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 //eux - 0x00003030
DATA 4 0x020e076c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS //eux - 0x00000030
//Data Strobes:
DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL //eux - 0x00020000 - diff mode ici???
DATA 4 0x020e04bc 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 //eux - 0x00000030
DATA 4 0x020e04c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 //eux - 0x00000030
DATA 4 0x020e04c4 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 //eux - 0x00000030
DATA 4 0x020e04c8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 //eux - 0x00000030
//Data:
DATA 4 0x020e0760 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE //eux - 0x00020000
DATA 4 0x020e0764 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS //eux - 0x00000030
DATA 4 0x020e0770 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS //eux - 0x00000030
DATA 4 0x020e0778 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS //eux - 0x00000030
DATA 4 0x020e077c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS //eux - 0x00000030
DATA 4 0x020e0470 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 //eux - 0x00020030 - CMOS inout vs
DATA 4 0x020e0474 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 //eux - 0x00020030 - CMOS inout vs
DATA 4 0x020e0478 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 //eux - 0x00020030 - CMOS inout vs
DATA 4 0x020e047c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 //eux - 0x00020030 - CMOS inout vs
//============================================================================
// DDR Controller Registers
//============================================================================
// Manufacturer: Micron
// Device Part Number: MT42L128M32D1
// Clock Freq.: 400MHz
// MMDC channels: MMDC0
// Density per CS in Gb: 4
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 14
// Column address: 10
// Data bus width 32
//============================================================================
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set eux - 0x00008000 up
DATA 4 0x021b085c 0x1B4700C7 //MMDC0_MPZQLP2CTL,LPDDR2 ZQ params
//============================================================================
// Calibration setup.
//============================================================================
DATA 4 0x021b0800 0xA1390000 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ eux - 0xA1390000 calibration.
//ca bus abs delay
DATA 4 0x021b0890 0x00400000 // MMDC0_MPPDCMPR2 values of 20,40,50,60,7f tried. no difference seen Original Values (Delete Later) Difference?
//Read calibration
DATA 4 0x021b0848 0x40404040 // MPRDDLCTL PHY0
//Write calibration
DATA 4 0x021b0850 0x40404040 // MPWRDLCTL PHY0
//dqs gating disabled (always disable for LPDDR2)
DATA 4 0x021b083c 0x20000000 // MMDC0_MPDGCTRL0
DATA 4 0x021b0840 0x00000000 // MMDC0_MPDGCTRL1
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 Original Values (Delete Later) Difference?
DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 0x00009c40 0x33333333
DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 0x00000000 0x33333333
DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 0x00000000 0x33333333
//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4 0x021b082c 0xF3333333 // DDR_PHY_P0_MPREDQBY0DL3 Original Values (Delete Later) Difference?
DATA 4 0x021b0830 0xF3333333 // DDR_PHY_P0_MPREDQBY1DL3 0x00009c40 0xF3333333
DATA 4 0x021b0834 0xF3333333 // DDR_PHY_P0_MPREDQBY2DL3 0x00000000 0xF3333333
DATA 4 0x021b0838 0xF3333333 // DDR_PHY_P0_MPREDQBY3DL3 0x00000000 0xF3333333
// Complete calibration by forced measurement:
DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//============================================================================
// Calibration setup end
//============================================================================
// Channel0 - startng address 0x80000000
DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC eux - 0x0002002D
DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC eux - 0x00333030 //Not revelant in LPDDR2
DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 eux - 0x40435323
DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 eux - 0xB66E8D63
DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 eux - 0x01FF00DB
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4 0x021b0018 0x00001688 // MMDC0_MDMISC 0x015dc002 0x00001748 S2-S4
DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD //eux - 0x000026D2
DATA 4 0x021b0030 0x00000010 // MMDC0_MDOR //eux - 0x00431023
DATA 4 0x021b0038 0x00190778 // MMDC0_MDCFG3LP // only LPDDR2
DATA 4 0x021b0040 0x00000017 // Chan0 CS0_END
DATA 4 0x021b0400 0x11420000 // MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL
// Channel0 : Configure DDR device:
//CS0
DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
DATA 4 0x021b001c 0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=c2
DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4
DATA 4 0x021b001c 0x02038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6
DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF
DATA 4 0x021b0818 0x00000000 // DDR_PHY_P0_MPODTCTRL
DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled
DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) 0x01000202 0x00000000
Maybe you could try booting from NFS to discard some potential issue with the SD card reading that could lead to the CRC error?
Unfortunately, we do not have an ethernet available on our board. But we have a usb OTG if it is possible to load the kernel with it. I did not find anything for the kernel (I usualy use this with u-boot).
I tried several sd cards just in case but I am still getting the same error.
Thank you.
I found out the problem. It was only a missing define in the bootloader. I had to add the line:
#define BOOTZ
To have CRC correct.
Thank you Fabio for all your help!
T'en ai rendu ou Xavier alors ? Oublie pas ton résumé que tu dois nous rendre a chaque jour !
Yan Gagnon
President | CEO
GG Telecom
SPYPOINT and XCEL products
Le 2014-04-14 à 16:29, Xavier Boucher <admin@community.freescale.com> a écrit :
imx6 bootloader - kernel bad CRC
reply from Xavier Boucher in i.MX Community - View the full discussion
I found out the problem. It was only a missing define in the bootloader. I had to add the line:
#define BOOTZ
To have CRC correct.
Thank you Fabio for all your help!
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Do you mean?
#define CONFIG_CMD_BOOTZ
This one is used if you want to boot a zImage, which does not contain the embedded CRC.
Yes, this is the define. I do not understand myself but since adding this, I am able to have good CRC on the linux kernel.