1.
If it is Your own design, please check the board regarding PCB layout recommendations
in "Hardware Development Guide for i.MX 6 ..." . In particular :
"For SD module interfaces:
– Match data and CMD trace lengths (length delta depends on bus rates)
– CLK should be longer than the longest signal in the Data/CMD group (+5 mils)
— Similar DDR rules must be followed for data, address and control as for SD module inter".
2.
Also, please try to check the memory
“i.MX6 DDR Stress Test Tool V1.0.3”
https://community.freescale.com/docs/DOC-96412
Have a great day,
Yuri
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