iMx6 EIM parallel NOR Flash slow speed

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iMx6 EIM parallel NOR Flash slow speed

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sijilcv
Contributor II

We have a custom iMx6 Dual Plus board with EIM parallel NOR flash interfaced (32MB S29GL256S90DHI02), the uboot,kernel image and DTB is stored in this memory.
We managed to boot the device from NOR flash and load the kernel image and DTB to RAM from NOR flash. The RFS is kept inside eMMC memory.

The issue we are facing is the copying of kernel image from NOR to RAM is taking to much time. The NOR flash is a parallel flash with 16 bit data bus.
The performance is worst at u-boot level at kernel level the throughput is around 15.5 MByte/s still slow expected ( 80 MB/s)

In linux the EIM clock speed is at 132Mhz

cat /sys/kernel/debug/clk/eim_slow/clk_rate
132000000

U- boot
=> clocks
PLL_SYS 792 MHz
PLL_BUS 528 MHz
PLL_OTG 480 MHz
PLL_NET 125 MHz

IPG 66000 kHz
UART 80000 kHz
AHB 132000 kHz
AXI 264000 kHz
DDR 528000 kHz
USDHC1 198000 kHz
USDHC2 198000 kHz
USDHC3 198000 kHz
USDHC4 198000 kHz
EMI SLOW 66000 kHz
IPG PERCLK 66000 kHz

In U-boot I could see the EMI SLOW clock is at 66 Mhz is this need to be corrected to 132Mhz. Is this to be done as part of DCD ?
What all things needs to be take care to get the optimal performance of the NOR flash. ?

As per the application note from cypress (AN98562) the following are the configuration

EIM.png

Is XIP supported by IMx6  ?

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fabio_estevam
NXP Employee
NXP Employee

It does not use DMA.  You can try to implement DMA support. What is the throughput you are getting after switching to memcpy()?

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sijilcv
Contributor II

Hi we are planing to move the NOR from 16 bit to 32 bit bus width do you have any suggestions ? Can we expect double throughput ?

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sijilcv
Contributor II

Now the through put is about 37.5 MByte/s with assembly memcpy function.

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fabio_estevam
NXP Employee
NXP Employee

On mx6qsabreauto I see the emi clock as 132MHz. Please make sure you are using a modern version of U-Boot.

How are you copying the kernel and dtb from NOR flash to RAM? Are you using the U-Boot "cp" command?

I have recently changed the "cp" command implementation in U-Boot so that it can use the optimized assembly memcpy() library. It does significantly increase the performance of the "cp" command.

Please find attached the four patches below:

https://www.mail-archive.com/u-boot@lists.denx.de/msg234197.html 

https://www.mail-archive.com/u-boot@lists.denx.de/msg234180.html 

https://www.mail-archive.com/u-boot@lists.denx.de/msg234198.html 

https://www.mail-archive.com/u-boot@lists.denx.de/msg234179.html 

Let me know if it helps for you.

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sijilcv
Contributor II

Is this assembly memcpy() uses DMA. if no can we use DMA copy for NOR FLASH read for better performance ? 

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sijilcv
Contributor II

Yes I am using cp command ? I will try the following patches and let you know the result.

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fabio_estevam
NXP Employee
NXP Employee

Also, by default register 20C_401C (CCM_CSCMR1) has:

Field: clk_eim_slow_sel : 00 -->derive clock from AXI clk root

aclk_eim_slow_podf" 01 --> divide by 2

So AXI clk in your case is 264 MHz, so EMI_SLOW should be: 264/2 = 132 MHz.

Please configure CCM_CSCMR1 correctly so that is can generate a 132MHz EMI clock.

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fabio_estevam
NXP Employee
NXP Employee

Ok, just checked the MX6DQP Reference Manual. The aclk_eim_slow_podf field by default is 0x3 --> which means divide by 4, so 264 / 4 = 66 MHz. On mx6q the aclk_eim_slow_podf field by default is 0x1 --> divide by 2.

So what you need to do is configure the aclk_eim_slow_podf field to 1 in your board file. Then you will have 132MHz for EIM clock.

With this change plus the series I pointed you at above I believe you will have a much better EIM throughput.

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fabio_estevam
NXP Employee
NXP Employee

I don't have my mx6qsabreauto nor mx6qpsabreauto handy, but the following patch makes sure the EIM clock is setup correctly on both cases. Please give it a try and let me know if you can get EIM clock at 132MHz in U-Boot. You would probably need to adapt it to your board, but that will be simple.

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igorpadykov
NXP Employee
NXP Employee

Hi sijil

maximum operating frequency for EIM data transfer is 104 MHz according

to sect.4.9.3 External Interface Module (EIM) i.MX6DQP Datasheet

http://www.nxp.com/files-static/32bit/doc/data_sheet/IMX6DQPCEC.pdf 

it could be adjusted tweaking parent pll frequency and using description in

Chapter 18 Clock Controller Module (CCM) i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf.

EIM xip is supported, it is necessary to configure appropriately addresses in ivt table

given in Figure 8-21. Image Vector Table RM.

Best regards
igor
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