imx6dl: eim: muxed async read - when are the data lines sampled

[lzenz]

Hello,

i have already managed to read with the #eim parallel address/data bus from a fpga. We use a #muxed #async configuration of the bus.

When does the #imx6dl eim sample the data lines during a read operation? (after CS assertion?, after OE assertion? Which BLCK edge?)

How many samples are required?

Thank You.

Best regards,

Ludwig

[lzenz]

I found this already, but how can I customize the bus configuration to concern this WE43 value?

When is the data sampled?

Best regards,

Ludwig

[igorpadykov]

please refer to

linux/Documentation/devicetree/bindings/bus/imx-weim.txt

Best regards
igor

[lzenz]

I am familiar with this, too.

There is WE43 not mentioned and there is not Information about the sampling of the data lines during read.

Can you please answer this questions?

When does the #imx6dl eim sample the data lines during a read operation? (after CS assertion?, after OE assertion? Which BLCK edge?)

How many samples are required?

[igorpadykov · Accepted solution]

eim samples the data lines during a read operation at CS rising edge,
data should be valid before CS assertion at WE43 time depicted on
Figure 19. Asynchronous Memory Read Access i.MX6SDL Datasheet.

To meet timings one can adjust register EIM_CSnRCR1, RWSC,RCSA,RCSN
described in sect.22.9.3 Chip Select Read Configuration Register 1 (EIM_CSnRCR1)

i.MX6SDL Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Best regards
igor

[lzenz]

hello igor,

thank you very much for your answer. This is the information i needed.

I have one problem: It doesn't match the behavior i observed. If had to make a guess i would say it is sampled on each BLCK rising edge until CS rising edge.

Please have a look at my measurements i have attached. The timing from measurement max_RWSC_10.png does work as i expect. The timing in fail_RWSC_9.png does not work. There is only one difference in the timings: RWSC is 10 or 9.

green: D0

violet: A0 (hold via address latch)

light blue: OE (read)

yellow: CS

Marker B is at the point where out fpga puts valid data on the data lines. In both cases at rising edge of CS is valid data on the data lines available.

Any ideas?

Thank you very much.

Best regards,

Ludwig

[igorpadykov]

Hi Ludwig

BCLK signal is not used in asynchronous mode

Best regards
igor

[lzenz]

Hello igor,

i know BCLK is not part of the interface signals when I run in asynchronous mode. Maybe I should have written WEIM CLK.

Please focus an that:

Do you have a explanation for the behaviour i observe?

Please have a look at my measurements.

Best regards,

Ludwig

[lzenz]

I think I've got it!

It is because of delays within our FPGA and where i did the measurements.

Thank you for supporting me.

Best regards,

Ludwig

[igorpadykov]

Hi Ludwig

please refer to parameter WE43 Input Data Valid to EIM_CSx in

Figure 19. Asynchronous Memory Read Access i.MX6SDL Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf

Best regards
igor
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