refer to your sensor data, it seems csis-hs-settle = <31>; is too high, pls refer to the table as below and set the correct data
I understood that for my data-rate 1440Mbps/lane implies clock-rate 720MHz, then I also tried with csis-hs-settle=15 and csis-hs-settle=16 and neither worked.
From the following discussion : https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-r... with the answer of you colleague :
I understood differently : for clock freq 720MHz --> value in the table should 720 * 2 = 1440MHz then csis-hs-settle=31. What do you think?
Regards,
Khang
Hi @joanxie ,
I saw your advice about the `assign-clock-rates` for MIPI-CSI2 from following discussion : https://community.nxp.com/t5/i-MX-Processors/CSI-transfer-rates-and-limitations/m-p/995950
For being able to capture 4K, would it still be valid for the BSP-5.4.70-2.3.2 that I am using seeing the configuration of mipi_csi nodes are as below (arch/arm64/boot/dts/freescale/imx8mp.dtsi) :
mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket0>;
gpr = <&mediamix_blk_ctl>;
no-reset-control;
power-domains = <&mipi_phy1_pd>;
status = "disabled";
};
mipi_csi_1: csi@32e50000 {
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
assigned-clock-rates = <266000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket1>;
gpr = <&mediamix_blk_ctl>;
no-reset-control;
power-domains = <&mipi_phy2_pd>;
status = "disabled";
};
Thanks in advance and best regards,
Khang
