How to compute S_CLKSETTLECTL value for MIPI CSI-2 receiver (on i.MX8M Mini)

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How to compute S_CLKSETTLECTL value for MIPI CSI-2 receiver (on i.MX8M Mini)

Contributor I


I'm trying to bring up camera support on an i.MX8M Mini board with an ON Semiconductor MT9M114 camera sensor. I'm facing a number of different problems, which I'll bring up in different threads to keep the discussion flow focussed and readable.

The first issue is related to the configuration of the D-PHY Ths-settle and Tclk-settle parameters, set respectively in the HSSETTLE and S_CLKSETTLECTL fields of the MIPI_CSI_DPHY_COMMON_CTRL register. The reference manual documents those fields as follows:


HS-RX settle time control
Slave Clock Lane Control for Ths-settle


Slave clock lane control for Tclk-settle
2'b0x - 110ns to 280ns (v0.87 to v1.00)
2'b10 - 150 ns to 430ns (v0.83 to v0.86)
2'b11 - 60 ns to 140ns (v0.82)


More information regarding the HSSETTLE and S_CLKSETTLECTL fields has been supplied in this forum, at The S_CLKSETTLECTL value is however incorrect.

To debug the issue, I have acquired an i.MX8M Mini EVK with an OV5640 camera module, and run the official imx_5.4.70_2.3.0 kernel branch, without modification. The device tree specifies the S_CLKSETTLECTL parameter through the csis-clk-settle property, and sets it to 2:

&mipi_csi_1 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        port {
                mipi1_sensor_ep: endpoint@1 {
                        remote-endpoint = <&ov5640_mipi1_ep>;
                        data-lanes = <2>;
                        csis-hs-settle = <13>;
                        csis-clk-settle = <2>;

                csi1_mipi_ep: endpoint@2 {
                        remote-endpoint = <&csi1_ep>;

This allows me to correctly capture frames from the OV5640. However, if I set csis-clk-settle to 0, no frames are produced by the device (the driver doesn't signal any buffer being completed). The S_CLKSETTLECTL value this makes a difference.

My main question is: how should the S_CLKSETTLECTL value be selected for a sensor, based on its D-PHY clock lane frequency ?

The side question is: in the reference manual, what does the version number listed in the S_CLKSETTLECTL documentation (v0.82, v0.83 to v0.86, v0.87 to v1.00) correspond to ?

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4 Replies

NXP TechSupport
NXP TechSupport

The configuration of MIPI CSI-2 on the CPU side is determined by the camera you are using.
If the version of MIPI CSI-2 of your camera is v0.83 to v0.86, S_CLKSETTLECTL[1:0]=2,
if the version of MIPI CSI-2 of your camera is V0.82, S_CLKSETTLECTL[1:0]=3,
if you The MIPI CSI-2 version of the camera is v0.87 to v1.00, S_CLKSETTLECTL[1:0]=0;
if the MIPI CSI-2 version of your camera is V1.2, S_CLKSETTLECTL[1:0]= 0.


In other words, we must tell the CPU's MIPI CSI-2, which version of the camera's MIPI CSI-2.




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NXP TechSupport
NXP TechSupport

Hi ,

See below, please!

>>how should the S_CLKSETTLECTL value be selected for a sensor, based on its D-PHY clock lane frequency ?
It's value is determined by the MIPI CSI-2 VERSION OF your camera.
v0.87 to v1.00 --- > S_CLKSETTLECTL[1:0]=0
v0.83 to v0.86-----> S_CLKSETTLECTL[1:0]=2
v0.82 -- >S_CLKSETTLECTL[1:0]=3

>>About MIPI CSI-2 clock frequency
MIPI CSI-2 of CPU side must know camera's mipi clock , then configure itself.
In other words, MIPI CSI-2 of CPU side configures its own registers according to the camera's clock.


For i.MX8M MINI CSI-2:


for other frequencies, they are the same as those of i.MX7D, listed on the link:


Hope this information is helpful to you.

Have a nice day!



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Contributor II


On iMX 8M Mini, my IMX258  sensor's documentation says ("MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) version 1.10" and "D-PHY version 1.1") so in that case you recommend the csis-clk-settle to be 0?

Best regards,


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Contributor I

Hello Weidong,

Thank you for your reply.

When you mention the MIPI CSI-2 version, do you mean the MIPI D-PHY version ?

The OV5640 documentation doesn't state a particular D-PHY version unfortunately. It however documents the registers that configure the MIPI D-PHY timings. Tclk-prepare is set to 60ns, and Tclk-zero to 390ns. Tclk-prepare+Tclk-zero is thus equal to 450ns. This is compliant with D-PHY v1.00 that requires Tclk-prepare to be between 38ns and 95ns, and Tclk-prepare+Tclk-zero to be at least 300ns. This is also compliant with the times given in the i.MX8MM reference manual for S_CLKSETTLECTL = 0 (110ns to 280ns). It is not compliant with S_CLKSETTLECTL = 2 (150ns to 430ns). However, setting S_CLKSETTLECTL to 0 doesn't work, and setting S_CLKSETTLECTL to 2 does. What am I missing ?

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