Hi NXP,
Our team want to design the ethernet as follow, Is it possible controlling ethernet by this method ?
M7 use the serial interface(SPI/QSPI) sending PHY configuration data to FPGA, the FPGA will control the PHY MIDO/MDC by M7's PHY data.
Thanks.
FPGA - MDIO/MDC
M7 - RGMII TX / RGMII RX
- SERIAL INTERFACE (SPI, QSPI)
Best Regards,
Wayne.
