IMX8QM CSI HS_SETTLE parameter (AN13573 question)

[akochubey]

Hi All,

I've a question regarding application note AN13573 (AN13573 - i.MX 8/RT MIPI DSI/CSI-2) on computing HS_SETTLE parameter value for MIPI CSI2 receiver.

AN13573 says:

-------------------------

6.1.5 D-PHY setup
The only D-PHY parameter that needs configuration is the T HS-SETTLE .

In this example, RxClkInEsc and CLK_UI (pixel clock) are both 60 MHz. The time period for both is 1/60 MHz = 16.67 ns.

The D-PHY specification requires the T HS-SETTLE to be in the range of 85 ns + 6 * UI to 145 ns + 10 * UI. This calculation works out to a range of 185 ns – 311.67 ns.

For the RT1170, the equation for programming T HS-SETTLE is:

T_HS_SETTLE = PRG_RXHS_SETTLE + 1 * Tperiod of RxClkInEsc

-------------------

as it can be seen, calculations above uses clock period of 60 MHz CLK_UI as "UI" value. But AN13573 says CLK_UI is a clock, originating from IMX8 and used to read out values from CSI receiver to the rest of the chip:

--------------

5.6.2 Pixel clock
SOC generates the PIXEL_CLK . PIXEL_CLK must be set so that image bandwidth exiting the CSI-2 block is greater than or equal to the image bandwidth entering the block. The 28FDSOI parts refer to this clock as the user-interface clock or CLK_UI

-------------

This seems weird. It comes to that Ths_settle calculation is only based on internal clocks of IMX8 whereas it should be conformant to both CSI devices (both transmitter and receiver).

Shouldn't UI in the formula above to a period of high-speed lane clock (168 MHz in the example), giving Ths_settle limits 121-205 ns?

Dear NXP staff, please would you advise on that, because

Unfortunately, a related question https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-r... doesn't shed light on the "UI" (interesting, the table there uses lane data rate as a basis, not the internal CLK_UI).

Unfortunately, IMX8QM Reference Manual (Rev. 0, 9/2021) doesn't say anything about HS_SETTLE at all, except saying it is in bits 9:4 in PHY_CTRL register.

Unfortunately, there is no suitable comments in imx8-mipi-csi2.c driver code. It uses "UI = 1000 / mipi csi phy clock" as a basis for calculation (see calc_hs_settle), but it is not clear what does it mean and looks contradictory to AN13573.

Unfortunately, my another question (https://community.nxp.com/t5/i-MX-Processors/IMX8QM-CSI-clocks-AN13573-question-on-CLOCK-ROOT73/m-p/...) regarding CSI clocks is not yet answered. I can see that Escape clock (used for Ths_settle calculation) is 72 MHz for me (IMX8QM), but I've no idea if this is right or not.

Unfortunately, based on what I see on this forum, it seems that I'm not alone, having bad time with CSI receiver, so any correct information would be greatly appreciated.

Please would you advise on that.